EP0452091B1
Expired / Lapsed
EP
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Electrically programmable antifuse element and method of forming it
Assignee: Microsemi SoC Corp
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Filing: 1991-04-09
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Granted: 1996-11-13
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Expires: 2011-04-09
Abstract
Abstract An electrically programmable antifuse element incorporates a composite interlayer of dielectric material and amorphous silicon interposed between two electrodes. The lower electrode may be formed from a refractory metal such as tungsten. Preferably, a thin layer of titanium is deposited over the tungsten layer and its surface is then oxidized to form a thin layer of titanium oxide which serves as the dielectric material of the composite dielectric/amorphous silicon interlayer. A layer of amorphous silicon is then deposited on top of the titanium oxide dielectric to complete the formation of the composite interlayer. A topmost layer of a refractory metal such as tungsten is then applied over the amorphous silicon to form the topmost electrode of the antifuse. <IMAGE>
Inventors
- 👤 John L. Mccollum
- 👤 Shih-Ou Chen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 21:00
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491; H10W20/41; H10W20/425
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
95 words
An electrically programmable antifuse element disposed on a semiconductor substrate (10) in an integrated circuit, the element comprising: a first electrode (16) formed on said substrate, a dielectric layer (24) disposed over said first electrode, an amorphous silicon layer (26) disposed over said dielectric layer, and a second electrode (28) disposed over said layer of amorphous silicon; characterised in that: said first electrode (16) comprises a first layer (18) of a refractory metal and a layer (20) of titanium over said first layer and said dielectric layer (24) consists of a layer of titanium dioxide.
Claim 2
Dependent Claim
30 words
An electrically programmable antifuse element according to claim 1, further including a layer of arsenic doped polysilicon (30) in between said dielectric layer (24) and said amorphous silicon layer (26).
Claim 3
Dependent Claim
33 words
An electrically programmable antifuse element according to claim 2, wherein said layer of arsenic-doped polysilicon (30) has a thickness in the range of from between 50 nm to 250 nm (500 to 2500Å).
Claim 4
Dependent Claim
42 words
An electrically programmable antifuse element according to claim 1, 2 or 3, wherein said first electrode (16) is electrically connected to a diffusion region (12) within said substrate (10), said diffusion region having a conductivity type opposite to that of said substrate.
Claim 5
Dependent Claim
34 words
An electrically programmable antifuse element according to any one of the preceding claims, wherein said layer of titanium (20) has a thickness in a range from 10 nm to 100 nm (100Å to 1000Å).
Claim 6
Dependent Claim
30 words
An electrically programmable antifuse element according to any preceding claim, wherein said amorphous silicon layer (26) has a thickness of from about 100 nm to 250 nm (1000Å to 2500Å).
Claim 7
Dependent Claim
29 words
An electrically programmable antifuse element according to any preceding claim, wherein said second electrode (28) comprises a refractory metal having a thickness of from 100 nm (1000Å) to 2µm.
Claim 8
Dependent Claim
38 words
An electrically programmable antifuse element according to any one of the preceding claims, wherein said dielectric layer (24) of titanium oxide has a thickness in the range of from about 5 nm to 15 nm (50Å to 150Å).
Claim 9
Dependent Claim
30 words
A semiconductor device disposed on a semiconductor substrate including a plurality of electrically programmable low impedance antifuse elements, each of said antifuse elements being in accordance with any preceding claim.
Claim 10
Independent Claim
165 words
A method of forming an electrically programmable, low impedance antifuse element on a semiconductor substrate (10) comprising the steps of: forming a first electrode (16) over a selected portion of said substrate, forming an insulating layer (22) over said first electrode, forming an opening in said insulating layer to create an exposed portion of said first electrode in a region where said antifuse element is to be located, forming a dielectric layer (24) over said exposed portion of said first electrode layer, forming an amorphous silicon layer (26) over said dielectric layer, and forming an upper electrode (28) over said amorphous silicon layer; characterised in that: said step of forming a first metal electrode includes the steps of: forming a first refractory metal layer (18) over said portion of the substrate, and forming a second layer (20) of titanium over said first refractory metal layer; and in that: said step of forming a dielectric layer (24) comprises oxidising the exposed surface of said titanium layer.
Claim 11
Dependent Claim
31 words
A method according to claim 10, wherein an arsenic doped polysilicon layer (30) is formed over said dielectric layer and said amorphous silicon layer is formed over said arsenic-doped polysilicon layer.
Claim 12
Dependent Claim
50 words
A method according to claim 10 or 11 including, before the step of forming said first electrode, the step of: selectively implanting a diffusion region (12) in said substrate having a conductivity type opposite to that of said substrate, and later electrically connecting said first electrode to said diffusion region.
References Cited (Backward Citations)
No citation records indexed.
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