Abstract An electronically programmable gate array comprises a plurality of rows of logic cells with each cell having a plurality of inputs, at least one output, and a plurality of electronically programmable voltage levels for configuring the cell. A plurality of sets of interconnect lines are formed in the array with one set of interconnect lines provided between adjacent rows of logic cells with electronically programmable contacts connecting inputs and an output of each cell in a row of cells with two adjacent sets of interconnect lines. Each row of logic cells preferably includes alternating three-input cells and two-input cells. Each electronically programmable voltage level comprises two voltage alterable resistors serially connected between first and second voltage potentials. Each electronically programmable interconnect comprises a voltage alterable resistor.
An electronically programmable gate array comprising a plurality of rows of logic cells, each row of logic cells includes alternating three-input cells of programmable gates and two-input cells of programmable gates, each cell having a plurality of inputs, at least one output, and a plurality of electronically programmable voltage levels for configuring the cell, wherein each electronically programmable voltage level comprises two voltage alterable resistors serially connected between first and second voltage potentials, and a plurality of sets of interconnect lines, one set of interconnect lines provided between adjacent rows of logic cells with electronically programmable means connecting inputs and an output of each cell in a row of cells with either of two adjacent sets of interconnect lines, each electronically programmable means comprises a voltage alterable resistor.
Claim 2
Dependent Claim
128 words
An electronically programmable gate array comprising a plurality of rows of logic cells, each row of logic cells includes alternating three-input cells of programmable gates and two-input cells of programmable gates, each cell having a plurality of inputs, at least one output, and a plurality of electronically programmable voltage levels for configuring the cell, wherein each electronically programmable voltage level comprises two voltage alterable resistors serially connected between first and second voltage potentials, and a plurality of sets of interconnect lines, one set of interconnect lines provided between adjacent rows of logic cells with electronically programmable means connecting inputs and an output of each cell in a row of cells with either of two adjacent sets of interconnect lines, each electronically programmable means comprises a voltage alterable resistor.
Claim 3
Dependent Claim
62 words
The electronically programmable gate array as defined by claim 1 wherein each two-input logic cell is programmable for the following functions: 2-IN OR 2-IN AND 2-IN IAND 2-IN IOR 2-IN EXOR 2-IN EXNOR INVERTER D-TYPE LATCH and each three-input logic cell is programmable for the following functions: 2-IN OR 2-IN NOR 2-IN AND 2-IN NAND 2-IN EXOR 2-IN EXNOR 3-IN MUX INVERTER.