US4943538A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable low impedance anti-fuse element
Assignee: Microsemi SoC Corp
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Filing: 1988-03-10
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Granted: 1990-07-24
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Expires: 2008-03-10
Abstract
Abstract An electrically programmable low impedance circuit element is disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The electrically programmable low impedance circuit element of the present invention includes a lower conductive electrode which may be formed of a metal or semiconductor material, an insulating layer, which, in a preferred embodiment includes a first layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide. An upper electrode formed of a metal or of a semiconductor material of the same conductivity type of the lower electrode or a sandwich of both completes the structure.
Inventors
- 👤 Amr M. Mohsen
- 👤 Esmat Z. Hamdy
- 👤 John L. McCullum
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:21
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
153 words
A method for manufacturing a programmable low impedance anti-fuse element on a substrate in a CMOS fabrication process including the steps of: defining and doping with a first conductivity type, a first region in said substrate for forming the lower electrode of said programmable low impedance anti-fuse element simultaneously with a definition and doping of the source and drain regions in said substrate, removing the initial gate oxide layer in said first region, forming a dielectric layer for said programmable low impedance circuit interconnect element over said region, said dielectric layer including a first silicon dioxide portion, a second silicon nitride portion over said silicon dioxide portion, and a third silicon dioxide portion over said second silicon nitride portion, forming a conductive layer to form the upper electrode for said programmable low impedance circuit interconnect element over said dielectric layer, defining said conductive layer and said dielectric layer, continuing said CMOS process sequence.
Claim 2
Independent Claim
153 words
A method for manufacturing a programmable low impedance anti-fuse element on a substrate in a CMOS fabrication process including the steps of: defining and doping with a first conductivity type, a first region in said substrate for forming the lower electrode of said programmable low impedance anti-fuse element simultaneously with a definition and doping of the source and drain regions in said substrate, removing the initial gate oxide layer in said first region, forming a dielectric layer for said programmable low impedance circuit interconnect element over said region, said dielectric layer including a first silicon dioxide portion, a second silicon nitride portion over said silicon dioxide portion, and a third silicon dioxide portion over said second silicon nitride portion, forming a conductive layer to form the upper electrode for said programmable low impedance circuit interconnect element over said dielectric layer, defining said conductive layer and said dielectric layer, continuing said CMOS process sequence.
Claim 3
Dependent Claim
27 words
The method of claim 1 wherein the conductive layer forming the upper electrode is fabricated of polysilicon having a conductivity type the same as said first region.
Claim 4
Dependent Claim
36 words
The method of claim 1 including the further step of applying a voltage between said lower electrode and said upper electrode sufficient in magnitude to cause the formation of a conductive filament in said dielectric layer.
Claim 5
Independent Claim
99 words
A method of forming a programmable low impedance anti-fuse element in a bipolar fabrication process including the steps of: defining a region in the emitter for use as the lower electrode of said programmable low impedance anti-fuse element, forming a dielectric layer over said defined region, said dielectric layer including a first silicon dioxide portion, a second silicon nitride portion over said silicon dioxide portion, and a third silicon dioxide portion over said second silicon nitride portion, forming an upper electrode conductor region, defining said upper electrode conductor region and said dielectric region, continuing said bipolar fabrication process sequence.
Claim 6
Independent Claim
99 words
A method of forming a programmable low impedance anti-fuse element in a bipolar fabrication process including the steps of: defining a region in the emitter for use as the lower electrode of said programmable low impedance anti-fuse element, forming a dielectric layer over said defined region, said dielectric layer including a first silicon dioxide portion, a second silicon nitride portion over said silicon dioxide portion, and a third silicon dioxide portion over said second silicon nitride portion, forming an upper electrode conductor region, defining said upper electrode conductor region and said dielectric region, continuing said bipolar fabrication process sequence.
Claim 7
Dependent Claim
24 words
The method of claim 4 wherein said upper electrode conductor region is fabricated of polysilicon having a conductivity type the same as said emitter.
Claim 8
Dependent Claim
36 words
The method of claim 4 including the further step of applying a voltage between said lower electrode and said upper electrode sufficient in magnitude to cause the formation of a conductive filament in said dielectric layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-23 | 1994-01-22 | 1994-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-23 | 1998-01-22 | 1998-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-23 | 2002-01-22 | 2002-07-24 | $7700.00 | Window Closed / Lapsed |