US4502208A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making high density VMOS electrically-programmable ROM
Assignee: Texas Instruments Inc
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Filing: 1983-08-26
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Granted: 1985-03-05
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Expires: 2003-08-26
Abstract
Abstract A method of making an electrically-programmable memory array in which the memory elements are capacitor devices formed in anisotropically etched V-grooves, providing enhanced dielectric breakdown at the apex of the groove. After breakdown, a memory element exhibits a low resistance to a grounded substrate. The method includes forming access transistors in series with the memory elements, and polycrystalline silicon, deposited to form control gates of the access transistors, also forms address lines. Oxide is formed in the V-groove thinner than the gate oxide thickness formed for the access transistor, providing a lower programming voltage. These factors provide a very small, high speed device.
Inventors
- 👤 Roger K. McPherson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:15
CPC Classifications
H; H10; H10B; H10B41/00; G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; H10B69/00; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
94 words
A method of making an electrically programmable semiconductor device in a face of a semiconductor body comprising the steps of: etching said face of the semiconductor body anisotropically to provide a V-shaped groove in said face, growing a thin oxide dielectric layer in said groove, applying a conductive layer over the dielectric layer, connecting a voltage to said conductive layer of magnitude sufficient to breakdown said dielectric layer at the apex of the groove resulting in a low resistance conductive path from the conductive layer to the face of the body below such apex.
Claim 2
Independent Claim
94 words
A method of making an electrically programmable semiconductor device in a face of a semiconductor body comprising the steps of: etching said face of the semiconductor body anisotropically to provide a V-shaped groove in said face, growing a thin oxide dielectric layer in said groove, applying a conductive layer over the dielectric layer, connecting a voltage to said conductive layer of magnitude sufficient to breakdown said dielectric layer at the apex of the groove resulting in a low resistance conductive path from the conductive layer to the face of the body below such apex.
Claim 3
Dependent Claim
20 words
A method according to claim 1 including the step of growing an epitaxial layer on said face before said etching.
Claim 4
Independent Claim
102 words
A method of making an electrically-programmable semiconductor element at a face of a semiconductor body comprising the steps of: etching said face anisotropically to provide a recess in said face having a sharp edged breakdown area, growing a thin oxide dielectric layer at said breakdown area of said face, applying a conductive layer over said dielectric layer, applying a voltage between said conductive layer and another area of said face to thereby break down the dielectric layer at said breakdown area, resulting in a low resistance conductive path from the conductive layer to the face of the body at said breakdown area.
Claim 5
Independent Claim
102 words
A method of making an electrically-programmable semiconductor element at a face of a semiconductor body comprising the steps of: etching said face anisotropically to provide a recess in said face having a sharp edged breakdown area, growing a thin oxide dielectric layer at said breakdown area of said face, applying a conductive layer over said dielectric layer, applying a voltage between said conductive layer and another area of said face to thereby break down the dielectric layer at said breakdown area, resulting in a low resistance conductive path from the conductive layer to the face of the body at said breakdown area.
Claim 6
Dependent Claim
58 words
A method according to claim 3 including the steps of doping said body to a high concentration of impurity and then growing an epitaxial layer on said face of the body at a low concentration of impurity, and wherein said step of growing a dielectric layer is at a breakdown area where said epitaxial layer has been removed.
Claim 7
Dependent Claim
19 words
A method according to claim 4 wherein said epitaxial layer at said breakdown area is removed by anisotropic etching.
Claim 8
Dependent Claim
29 words
A method according to claim 3 wherein said step of applying a voltage includes controlling an insulated gate field effect transistor at said face to render such transistor conductive.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-03-04 | 1988-09-03 | 1989-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-04 | 1992-09-03 | 1993-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-04 | 1996-09-03 | 1997-03-05 | $7700.00 | Window Closed / Lapsed |