VMOS Read only memory

Claim 3

A method according to claim 1, wherein a plurality of other transistors and a plurality of contacts and interconnections are formed on said face peripheral to the array, wherein the step of programming uses a mask comprising a thick coating of silicon oxide applied at a low temperature compared to diffusion temperature, and wherein the step of programming uses a mask applied after said contacts and interconnections have been formed.

Claim 4

A method according to claim 1, wherein the step of programming uses a mask comprising a coating of photoresist.

Claim 5

A method of claim 1, wherein the field effect transistors and the other transistors are N-channel silicon gate transistors, and contacts and interconnections are formed peripheral to the array by metal deposited in a thin film and patterned.

Claim 6

A method according to claim 4, wherein the programming step is after the metal is deposited and patterned, and wherein the semiconductor body is P-type silicon, the sources and drains are N-type, and the ion implant is P-type.

Claim 7

A read only memory array comprising: a plurality of memory cells formed at a face of a silicon body in an array of rows and columns; each memory cell being formed in an anisotropically etched V-groove and including an insulated gate field effect transistor having a source, a drain and a gate, the source being a buried heavily-doped region common to a plurality of the transistors, the gate being insulated from the silicon by a gate insulator along the sidewalls of the V-groove; a plurality of other insulated gate field effect transistors formed at said face of the silicon body in an area peripheral to the array; a first thick silicon oxide insulating coating only on said area peripheral to the array covering the other field effect transistors except at contact areas; interconnections in the peripheral areas formed by metal strips on top of said first silicon oxide coating and connected to the other field effect transistors at said contact areas; and impurity implanted regions underlying the gate and gate insulator in the sidewalls of the V-grooves for selected ones of the memory cells to alter substantially the threshold of the transistors of such cells compared to the transistors of memory cells other than the selected ones.

Claim 8

A read only memory array comprising: a plurality of memory cells formed at a face of a silicon body in an array of rows and columns; each memory cell being formed in an anisotropically etched V-groove and including an insulated gate field effect transistor having a source, a drain and a gate, the source being a buried heavily-doped region common to a plurality of the transistors, the gate being insulated from the silicon by a gate insulator along the sidewalls of the V-groove; a plurality of other insulated gate field effect transistors formed at said face of the silicon body in an area peripheral to the array; a first thick silicon oxide insulating coating only on said area peripheral to the array covering the other field effect transistors except at contact areas; interconnections in the peripheral areas formed by metal strips on top of said first silicon oxide coating and connected to the other field effect transistors at said contact areas; and impurity implanted regions underlying the gate and gate insulator in the sidewalls of the V-grooves for selected ones of the memory cells to alter substantially the threshold of the transistors of such cells compared to the transistors of memory cells other than the selected ones.

Claim 9

A memory array according to claim 6, wherein a second thick insulating coating is formed on said face covering the array and the peripheral areas over the metal strips with apertures formed in the second insulating coating over only said selected ones of the memory cells.

Claim 10

A memory array according to claim 7, wherein the transistors in the array are N-channel silicon gate transistors, the sources being formed by a buried N+ region, the V-groove extending into the face of the buried N+ region, and the impurity implanted regions being ion implanted with boron to raise the threshold of the selected transistors.