Method of providing internal connections in a semiconductor device

Claim 2

A method as recited in claim 1, wherein said first and second patterns are produced by vapor depositing aluminum and said dielectric oxide layer consists essentially of aluminum oxide, said insulating layer which separates said patterns consisting essentially of silicon dioxide.

Claim 3

A method as recited in claim 1, wherein said dielectric oxide layer is electrolessly formed at surface regions of said first conductor pattern by dipping said substrate in an oxidizing bath.

Claim 4

A method as recited in claim 1, wherein said dielectric oxide layer is subjected to a stabilization treatment.

Claim 5

A method as recited in claim 1, wherein said dielectric oxide layer is formed by depositing an oxide originating from a reaction in the gaseous phase of an organo-metallic compound.

Claim 6

A method as recited in claim 1, wherein said dielectric oxide is selected from the group consisting of titanium oxide, tantalum oxide, hafnium oxide, zirconium oxide and niobium oxide.

Claim 7

A monolithic planar semiconductor device, comprising: a. a semiconductor substrate including at least one electronic circuit element at a major surface thereof; b. a first metallic conductor pattern disposed at said substrate surface, a portion of said pattern being electrically connected to a part of said circuit element; c. an apertured electrically insulating layer disposed over said surface and said first pattern, said aperture extending through said layer and being located at a part of said first pattern removed from said circuit element; d. a dielectric oxide layer disposed on said part of said first pattern, and e. a second metallic conductor pattern partially located on said dielectric oxide layer, other regions of said first and second patterns being separated by said electrically insulating film, said dielectric oxide layer having a breakdown voltage significantly less than said insulating layer.

Claim 8

A planar monolithic programmable memory matrix comprising semiconductor devices, said matrix comprising at least two metal conductor layers and an insulating layer disposed between said conductor layers, at least one of said devices being electrically connected to a portion of a first one of said Conductor layers, said insulating layer comprising a discontinuity extending completely therethrough to said first conductor layer at a point removed from said device, a dielectric oxide layer being disposed at said discontinuity between said conductor layers and between respective portions of said conductor layers located at said discontinuity, said dielectric layer being characterized by an electrical breakdown voltage significantly less than that of said insulating layer, portions of said conductor layers being available for electrical connection to a potential source, whereby said conductor layers are electrically connected to each other by applying therebetween an electrical potential exceeding said dielectric layer breakdown voltage.