Method in forming electrically continuous circuit through insulating layer

Claim 1

A method of fabricating a multilevel semiconductor device comprising the steps of: a. forming a plurality of components having regions thereof in a semiconductor body; b. forming a first insulating layer having a first plurality of apertures therein over selected regions of said components; c. forming a first level of metal conductors over said first insulating layer extending through said first apertures to interconnect appropriate regions of said components; d. forming a second insulating layer over said first level of metal conductors; e. forming a second plurality of apertures extending through both said first and second insulating layers to expose other selected regions on said components; f. immersing said semiconductor body in a solution containing a metallic salt; g. chemically reducing said salt from said solution and forming a metal conductor to substantially fill said second plurality of apertures and effect ohmic connection with said deposited metal over said other selected regions; and h. providing a second level of metal conductors selectively connecting said conductors formed by reducing said salt.

Claim 2

A method of fabricating a multilevel semiconductor device comprising the steps of: a. forming a plurality of components having regions thereof in a semiconductor body; b. forming a first insulating layer having a first plurality of apertures therein over selected regions of said components; c. forming a first level of metal conductors over said first insulating layer extending through said first apertures to interconnect appropriate regions of said components; d. forming a second insulating layer over said first level of metal conductors; e. forming a second plurality of apertures extending through both said first and second insulating layers to expose other selected regions on said components; f. immersing said semiconductor body in a solution containing a metallic salt; g. chemically reducing said salt from said solution and forming a metal conductor to substantially fill said second plurality of apertures and effect ohmic connection with said deposited metal over said other selected regions; and h. providing a second level of metal conductors selectively connecting said conductors formed by reducing said salt.

Claim 3

A method of fabricating a multilevel integratEd circuit array comprising the steps of: a. forming first and second semiconductor integrated circuits in a substrate, said integrated circuits having a first level of metal terminal pads connected to selected regions of components thereof; b. forming an insulating layer over said integrated circuits and substrate with apertures exposing selected ones of said metal terminal pads of said first and of said second integrated circuits; c. immersing said substrate in a metallic salt solution; d. chemically reducing said salt and forming a metal conductor to substantially fill said apertures and effect ohmic connection with said exposed selected metal terminal pads; and e. forming a second level of metal conductors selectively interconnecting said conductors formed by reducing said salt.

Claim 4

A method of fabricating a multilevel integratEd circuit array comprising the steps of: a. forming first and second semiconductor integrated circuits in a substrate, said integrated circuits having a first level of metal terminal pads connected to selected regions of components thereof; b. forming an insulating layer over said integrated circuits and substrate with apertures exposing selected ones of said metal terminal pads of said first and of said second integrated circuits; c. immersing said substrate in a metallic salt solution; d. chemically reducing said salt and forming a metal conductor to substantially fill said apertures and effect ohmic connection with said exposed selected metal terminal pads; and e. forming a second level of metal conductors selectively interconnecting said conductors formed by reducing said salt.