US3576549A
Expired / Lapsed
US
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Semiconductor device, method, and memory array
Assignee: Cogar Corp
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Filing: 1969-04-14
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Granted: 1971-04-27
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Expires: 1989-04-14
Abstract
Abstract This disclosure relates to a semiconductor device which has a first electrical state prior to the application of a particular voltage to at least one conductor thereof and a second, different, irreversible electrical state after the voltage was applied to the selected conductor. A method of forming an electrical contact is also disclosed which is achieved by breaking down a portion of the insulator of the semiconductor device by the application of a voltage to a conductor located on the insulator thereby permitting electrical contact to the semiconductor by the conductor. Additionally, a memory array is disclosed which permits a write-once, read-only function or operation by using an insulator breakdown technique to change semiconductor devices of the array from a first electrical state to a second, irreversible and different electrical state.
Inventors
- 👤 Martin S Hess
- 👤 Walter F Krolikowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 06:20
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; H; H10; H10D; H10D99/00; Y; Y10; Y10S; Y10S257/00; Y10S257/926
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
26 words
A semiconductor device in accordance with claim 1 wherein said thin insulating layer having a thickness in the range of about 50 to about 1,000 Angstroms.
Claim 2
Dependent Claim
26 words
A semiconductor device in accordance with claim 2 wherein said thin insulating layer having a thickness in the range of about 100 to about 600 Angstroms.
Claim 3
Dependent Claim
35 words
A semiconductor device in accordance with claim 1 wherein said voltage applied to said one conductor to break down the portion of said insulating layer locate beneath said one conductor being less than 100 volts.
Claim 4
Dependent Claim
42 words
A semiconductor device in accordance with claim 4 wherein said voltage applied to said oNe conductor to break down the portion of said insulating layer located beneath said one conductor being in the range of from about 5 to about 50 volts.
Claim 5
Dependent Claim
42 words
A semiconductor device in accordance with claim 5 wherein said voltage applied to said one conductor to break down the portion of said insulting layer located beneath said one conductor being in the range of from about 5 to about 30 volts.
Claim 6
Dependent Claim
37 words
A semiconductor device in accordance with claim 1 wherein said region of one type conductivity having a relatively low resistivity, said low resistivity region having an impurity concentration of at least 10 20 atoms per cubic centimeter.
Claim 7
Dependent Claim
19 words
A semiconductor device in accordance with claim 7 wherein said low resistivity region comprising the emitter of a transistor.
Claim 8
Dependent Claim
21 words
A semiconductor device in accordance with claim 1 wherein said low resistivity region and said one conductor comprising an underpass conductor.
Claim 9
Dependent Claim
19 words
A semiconductor device in accordance with claim 7 wherein said low resistivity region comprising a portion of a diode.
Claim 10
Dependent Claim
36 words
A semiconductor device in accordance with claim 1 wherein said region of one type conductivity being a relatively high resistivity, said high resistivity region having an impurity concentration of less than 1020 atoms per cubic centimeter.
Claim 11
Dependent Claim
16 words
A semiconductor device in accordance with claim 11 wherein said high resistivity region comprising a resistor.
Claim 12
Dependent Claim
19 words
A semiconductor device in accordance with claim 11 wherein said high resistivity region comprising a portion of a diode.
Claim 13
Dependent Claim
19 words
A semiconductor device in accordance with claim 11 wherein said high resistivity region comprising a collector of a transistor.
Claim 14
Dependent Claim
19 words
A semiconductor device in accordance with claim 11 wherein said high resistivity region comprising a collector of a transistor.
Claim 15
Dependent Claim
104 words
A semiconductor device in accordance with claim 1 wherein at least two conductors are located on said thin insulating layer, said voltage means applied to both of said two conductors to break down a portion of said insulating layer located beneath each of said two conductors, one of said two conductors being in ohmic contact with said region of one type conductivity after insulator breakdown, a region of opposite type conductivity from said region of one type conductivity forming a part of said substrate, the other of said two conductors being in ohmic contact with said region of opposite type conductivity after insulator breakdown.
Claim 16
Dependent Claim
140 words
A semiconductor device in accordance with claim 1 wherein at least three conductors are located on said thin insulating layer, said voltage means applied to each of said three conductors to breakdown a portion of said insulating layer located beneath each of said three conductors, one of said three conductors being in ohmic contact with said region of one type conductivity after insulator breakdown, a region of opposite type conductivity from said region of one type conductivity forming part of said substrate, sa second of said three conductors being in ohmic contact with said region of opposite type conductivity after insulator breakdown, a second region of the same conductivity type as said first region of one conductivity type, the third of said three conductors being in ohmic contact with said second region of said one conductivity type after insulator breakdown.
Claim 17
Dependent Claim
80 words
A semiconductor device comprising, in combination, a semiconductor substrate having regions of opposite type conductivity; a thin insulating layer located on one surface of said substrate; a plurality of conductors located on one surface of said thin insulating layer over said regions of opposite type conductivity; and voltage means connected to said conductors for applying a differential voltage to said conductors for breaking down the insulator portions beneath selected conductors to form at least one of active and passive devices.
Claim 18
Dependent Claim
24 words
A semiconductor device in accordance with claim 18 wherein one of said selecteD conductors being in electrical contact with a resistor after insulator breakdown.
Claim 19
Dependent Claim
24 words
A semiconductor device in accordance with claim 18 wherein one of said selected conductors being in electrical contact with a diode after insulator breakdown.
Claim 20
Dependent Claim
24 words
A semiconductor device in accordance with claim 18 wherein one of said selected conductors being in electrical contact with a transistor after insulator breakdown.
Claim 21
Dependent Claim
28 words
A semiconductor device in accordance with claim 18 wherein one of said selected conductors shorting out a PN junction between two of said regions of opposite type conductivity.
Claim 22
Dependent Claim
33 words
A semiconductor device in accordance with claim 18 wherein at least one of said plurality of conductors being in ohmic contact with at least one of said regions before and after insulator breakdown.
Claim 23
Dependent Claim
46 words
A semiconductor device in accordance with claim 18 wherein said thin insulating layer having a thickness in the range of from about 100 to about 600 Angstroms, said voltage applied to said selected conductors being in the range of from about 5 to about 30 volts.
Claim 24
Dependent Claim
140 words
A memory array comprising, in combination, a plurality of semiconductor devices interconnected to provide a memory array, each of said plurality of semiconductor devices comprising a semiconductor substrate having regions of opposite type conductivity, a thin insulating layer located on a surface of said substrate over said regions of opposite type conductivity, a plurality of conductors in contact with said thin insulating layer, writing means for writing information into said memory array by applying a differential voltage of a sufficient magnitude and duration to said conductors of a selected memory semiconductor device to break down the portion of said thin insulating layer located beneath at least one of said conductors for making electrical contact to said substrate to change the electrical nature of said selected memory device; and reading means for sensing the information contained in said monolithic memory array.
Claim 25
Dependent Claim
30 words
A memory array in accordance with claim 25 wherein at least one of said plurality of semiconductor devices comprising a resistor before insulator breakdown and a diode after insulator breakdown.
Claim 26
Dependent Claim
30 words
A memory array in accordance with claim 25 wherein at least one of said plurality of semiconductor devices comprising a resistor before insulator breakdown and a transistor after insulator breakdown.
Claim 27
Dependent Claim
34 words
A memory array in accordance with claim 25, wherein at least one of said plurality of semiconductor devices comprising a pair of back-to-back diodes before insulator breakdown and a single diode after insulator breakdown.
Claim 28
Dependent Claim
114 words
A memory array in accordance with claim 25 wherein said writing means comprising a first voltage source means electrically connected to each selected row of said array, said first voltage source means providing a voltage less than the voltage needed to break down the insulator portion located beneath said conductor, and a second voltage source means electrically connected to each selected column of said memory array, said second voltage source means providing a voltage less than the voltage needed to break down the insulator portion located beneath said conductor, said first and second voltage source means together providing the voltage amount needed to break down the insulator portion of said selected memory semiconductor device.
Claim 29
Dependent Claim
124 words
A memory array comprising, in combination, a plurality of semiconductor devices having regions of opposite type conductivity, an insulating layer located on a surface of said devices, a plurality of conductors in contact with said insulating layer and interconnected to provide a memory array, each of said semiconductor devices having a first electrical state prior to receiving a writing signal and an irreversible different second electrical state after receiving a writing signal; writing means electrically connected to said memory array for applying a differential voltage to said pluraLity of conductors for selecting at least one of said plurality of semiconductor devices and placing said selected semiconductor device in said second electrical state; and reading means for sensing the information contained in said memory array.
Claim 30
Dependent Claim
20 words
A memory array in accordance with claim 30 wherein said first electrical state of said semiconductor devices being a resistor.
Claim 31
Dependent Claim
16 words
A memory array in accordance with claim 31 wherein said second electrical state being a diode.
Claim 32
Dependent Claim
16 words
A memory array in accordance with claim 31 wherein said second electrical state being a transistor.
Claim 33
Dependent Claim
21 words
A memory array in accordance with claim 30 wherein said first electrical state being nonconducting, said second electrical state being conducting.
Claim 34
Dependent Claim
29 words
A memory array in accordance with claim 30 wherein said first electrical state being a nonconducting pair of back-to-back diodes, said second electrical state being a conducting single diode.
Claim 35
Dependent Claim
27 words
A memory array in accordance with claim 30 wherein said first electrical state exhibiting a passive device characteristic, said second electrical state exhibiting an active device characteristic.
References Cited (Backward Citations)
US3245051A
Cited
US3412220A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-26 | 1974-10-26 | 1975-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-26 | 1978-10-26 | 1979-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-26 | 1982-10-26 | 1983-04-27 | $7700.00 | Window Closed / Lapsed |