US3924265A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low capacitance V groove MOS NOR gate and method of manufacture
Assignee: American Microsystems Holding Corp
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Filing: 1973-08-29
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Granted: 1975-12-02
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Expires: 1993-08-29
Abstract
Abstract An MOS transistor is provided having a surface diffused drain and a common substrate source. A heavily doped base layer and a lightly doped space charge region are provided between the drain and source regions. The gate is formed on the inclined surface of a V groove which penetrates into the transistor to the substrate exposing the base layer to the gate structure. The gate is formed in the V groove by a silicon oxide insulative layer and conductive layer. Appropriate leads contact the gate conductor and the drain.
Inventors
- 👤 Thurman John Rodgers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:27
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H10; H10D; H10D84/00; H10D84/80; H10D84/811; H10D84/817; H10D84/82; H10D84/83; H10D84/83125; H10D84/837; H10D84/839; H10D99/00; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/512; H10D64/513; Y; Y10; Y10S; Y10S148/00; Y10S148/008; Y10S148/049; Y10S148/051; Y10S148/053; Y10S148/085; Y10S148/117
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
145 words
A FIELD EFFECT TRANSISTOR DEVICE, COMPRISING: AN N-TYPE SOURCE HAVING A DONOR DOPANT CONCENTRATION OF FROM ABOUT 10**17 TO ABOUT 5X10**19 ATOMS PER CUBIC CM AND HAVING A LOWER ACCEPTOR DOPANT CONCENTRATIONS; P-TYPE BASE MEANS OVERLYING THE SOURCE HAVING AN ACCEPTOR DOPANT CONCENTRATION LESS THAN THAN THE DONOR DOPANT CONCENTRATION OF THE SOURCE AND AN ACCEPTOR DOPANT CONCENTRATION PROFILE WHICH DECREASES WOTH DISTANCE FROM THE SOURCE, A DRIFT REGION OVERLYING THE BASE MEANS HAVING A DOPANT CONCENTRATION LESS THAN THE DOPANT CONCENTRATION IN THE BASE MEANS; N-TYPE DRAIN MEANS SELECTIVELY LOCATED IN THE DRIFT REGION; AT LEAST ONE V GROOVE EXTENDING INTO THE DEVICE EXPOSING A PORTION OF THE BASE MEANS AND THE DRIFT REGION; AN INSULATIVE LAYER OVERLYING THE EXPOSED PORTIONS; AT LEAST ONE CONDUCTOR OVERLYING AT LEAST A PORTION OF THE INSULATIVE LAYER; AND CONDUCTOR MEANS IN ELECTRICAL COMMUNICATION WITH THE DRAIN MEANS.
Claim 2
Dependent Claim
145 words
A FIELD EFFECT TRANSISTOR DEVICE, COMPRISING: AN N-TYPE SOURCE HAVING A DONOR DOPANT CONCENTRATION OF FROM ABOUT 10**17 TO ABOUT 5X10**19 ATOMS PER CUBIC CM AND HAVING A LOWER ACCEPTOR DOPANT CONCENTRATIONS; P-TYPE BASE MEANS OVERLYING THE SOURCE HAVING AN ACCEPTOR DOPANT CONCENTRATION LESS THAN THAN THE DONOR DOPANT CONCENTRATION OF THE SOURCE AND AN ACCEPTOR DOPANT CONCENTRATION PROFILE WHICH DECREASES WOTH DISTANCE FROM THE SOURCE, A DRIFT REGION OVERLYING THE BASE MEANS HAVING A DOPANT CONCENTRATION LESS THAN THE DOPANT CONCENTRATION IN THE BASE MEANS; N-TYPE DRAIN MEANS SELECTIVELY LOCATED IN THE DRIFT REGION; AT LEAST ONE V GROOVE EXTENDING INTO THE DEVICE EXPOSING A PORTION OF THE BASE MEANS AND THE DRIFT REGION; AN INSULATIVE LAYER OVERLYING THE EXPOSED PORTIONS; AT LEAST ONE CONDUCTOR OVERLYING AT LEAST A PORTION OF THE INSULATIVE LAYER; AND CONDUCTOR MEANS IN ELECTRICAL COMMUNICATION WITH THE DRAIN MEANS.
Claim 3
Dependent Claim
35 words
The device of claim 1, wherein the base means is continuously formed across the device, and the drain means is a plurality of separate drains forming a series of transistor devices having a common source.
Claim 4
Dependent Claim
34 words
The device of claim 1, wherein the intersection of the V-groove with the drain means and the intersection of the V-groove and the base means form perimeters around the V-groove in the sides thereof.
Claim 5
Dependent Claim
11 words
The device of claim 3, wherein the drift region is p-type.
Claim 6
Dependent Claim
21 words
The device of claim 4, wherein silicon oxide is selectively formed along the surface of the drain side of the device.
Claim 7
Dependent Claim
27 words
The device of claim 5, wherein a p-type channel stopping surface layer is formed along the drain side of the device and over the p-type drift region.
Claim 8
Dependent Claim
21 words
The device of claim 1, wherein a layer of silicon nitride is selectively formed over the drain surface of the wafer.
Claim 9
Dependent Claim
22 words
The device of claim 1, wherein the drift region is p-type and the substrate is n-type having a resistivity of 0.01 ohm-cm.
Claim 10
Dependent Claim
18 words
The device of claim 1, wherein the V groove passes through at least a portion of the substrate.
Claim 11
Dependent Claim
38 words
The device of claim 1, wherein a source conductive lead is mounted on the one surface of the wafer, and a drain conductive lead and a gate conductive lead are mounted on the other surface of the wafer.
Claim 12
Dependent Claim
13 words
The device of claim 1 wherein the V groove is etched to completion.
Claim 13
Dependent Claim
18 words
The device of claim 1, wherein the base means epitaxially interfaces with the source and the drift region.
Claim 14
Dependent Claim
16 words
The device of claim 1, wherein the V groove extends into the source of the device.
Claim 15
Dependent Claim
16 words
The device of claim 1, wherein the base means is less than a micron in thickness.
Claim 16
Dependent Claim
150 words
A NOR logic circuit, comprising: an n-type common source having a donor dopant concentration of from about 1017 to about 5 X 1019 atoms per cubic cm and a lesser acceptor dopant concentration; a p-type base region over the common source having an acceptor dopant concentration less than the donor dopant concentration of the common source and an acceptor dopant concentration profile which decreaseS with distance from the common source; a drift region over the base region having a dopant concentration less than the dopant concentration in the base region; at least one n-type drain over the drift region; at least one V groove extending through each drain and the drift region and the base region and extending into the common source; and gate means formed in the V groove by an insulative layer covered by a conductive layer for controlling the current from the common source to each drain.
Claim 17
Dependent Claim
150 words
A NOR logic circuit, comprising: an n-type common source having a donor dopant concentration of from about 1017 to about 5 X 1019 atoms per cubic cm and a lesser acceptor dopant concentration; a p-type base region over the common source having an acceptor dopant concentration less than the donor dopant concentration of the common source and an acceptor dopant concentration profile which decreaseS with distance from the common source; a drift region over the base region having a dopant concentration less than the dopant concentration in the base region; at least one n-type drain over the drift region; at least one V groove extending through each drain and the drift region and the base region and extending into the common source; and gate means formed in the V groove by an insulative layer covered by a conductive layer for controlling the current from the common source to each drain.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-01 | 1979-06-02 | 1979-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-01 | 1983-06-02 | 1983-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-01 | 1987-06-02 | 1987-12-02 | $7700.00 | Window Closed / Lapsed |