Mos integrated circuit with substrate containing selectively formed resistivity regions

Claim 1

An integrated circuit comprising a semiconductor p-type substrate of a predetermined impurity concentration, first and second p-type mesas formed on said substrate, a thick oxide region completely surrounding said second mesa and extending into a major surface of said substrate, a p-type diffused layer of a substantially higher impurity concentration and lower resistivity than said substrate formed on said substrate and underlying only said thick oxide region and in self-alignment therewith, first and second n-type spaced diffused regions formed in said first mesa and an insulated electrode thereover respectively defining the source and drain regions and gate electrode of a common active field effect device, first and second contiguous portions of one of said first and second diffused regions respectively coming into contact with said substrate and with said diffused layer, an additional n-type diffused region formed in said second mesa, said additional diffused region being non-related to said active field effect device, a metal conducting layer formed on said thick oxide region and overlying said diffused layer, said additional diffused region and said metal conducting layer forming a potential parasitic device and means For applying a reverse bias voltage to said substrate, whereby the field inversion voltage of said potential parasitic device is substantially increased without materially affecting the threshold voltage of said active device, and without significantly reducing the breakdown voltage at said diffused regions.