Method of fabricating integrated circuits with oxidized isolation and the resulting structure

Claim 2

Structure as in claim 2 wherein said substrate is of P-type conductivity.

Claim 3

Structure as in claim 2 wherein said substrate is of N-type conductivity.

Claim 4

Structure as in claim 3 wherein said substrate contains a plurality of low resistivity regions of N-type conductivity formed in the surface of said substrate directly beneath said epitaxial layer.

Claim 5

Structure as in claim 4 wherein said substrate contains a plurality of low resistivity regions of P-type conductivity formed in the surface of said substrate directly beneath said epitaxial layer.

Claim 6

Structure as in claim 1 wherein said substrate is of one type conductivity and said epitaxial layer is of the opposite type conductivity.

Claim 7

Structure as in claim 7 wherein said substrate contains a plurality of low resistivity regions of opposite type conductivity formed in the surface of said substrate directly beneath said epitaxial layer.

Claim 8

Structure as in claim 7 wherein said substrate contains a plurality of low resistivity regions of said one type conductivity formed in the surface of said substrate directly beneath said epitaxial layer.

Claim 9

Structure as in claim 7 wherein said substrate is of P-type conductivity.

Claim 10

Structure as in claim 7 wherein said substrate is of N-type conductivity.

Claim 11

Structure as in claim 1 wherein each pocket of epitaxial semiconductor material contains selected regions of differing conductivity type.

Claim 12

Structure as in claim 12 wherein said regions of differing conductivity type comprise active and passive semiconductor devices.

Claim 13

Structure as in claim 12 including regions of low resistivity formed in the underlying substrate to interconnect regions separated by oxidized isolation regions.

Claim 14

Structure as in claim 1 wherein said epitaxial layer has a thickness of less than 5 microns.

Claim 15

Structure as in claim 1 wherein said epitaxial layer has a thickness of 1.25 microns.

Claim 16

Structure as in claim 7 including a low resistivity first region of opposite conductivity type formed in said substrate adjacent to said epitaxial layer of semiconductor material, and a low resistivity second region of opposite conductivity type, said second region extending from the surface of said epitaxial layer into contact with said low resistivity first region, said second region being surrounded by an annular-shaped oxidized isolation region extending through said epitaxial layer to said first region in said substrate.

Claim 17

Structure as in claim 17 wherein said first region extends underneath a portion of said oxidized isolation region and into contact with another adjacent region of epitaxial silicon.

Claim 18

Structure as in claim 17 wherein said adjacent region of epitaxial silicon comprises: a collector region of opposite conductivity type contacting said first region; a base region of one conducitvity type extending to the annular-shaped oxidized isolation region surrounding said adjacent region of epitaxial silicon; and an emitter region formed of opposite conductivity type in said base region.

Claim 19

Structure as in claim 19 wherein said emitter region abuts a portion of the annular-shaped oxidized isolation region surrounding said adjacent epitaxial region of silicon.

Claim 20

Structure as in claim 20 wherein the surface of said epitaxial siliCon is covered by an insulating layer containing therein windows through which a separate first contact is made to each of said second region, said base region and said emitter region.

Claim 21

Structure as in claim 21 including a second contact to said second region and a third contact to said second region, said second and third contacts being separated by a selected distance thereby to form a resistive path from said second contact to said third contact through the said second region.

Claim 22

Structure as in claim 21 including a second contact to said base region and a third contact to said base region, said second and third contacts to said base region being separated by a selective distance thereby to form a base resistor between said second contact and said third contact to said base region.

Claim 23

Structure as in claim 21 wherein two windows are formed in the insulation overlying a pocket of epitaxial silicon thereby to form an epitaxial resistor from the epitaxial silicon between said two contacts.