US4748490A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Deep polysilicon emitter antifuse memory cell
Assignee: Texas Instruments Inc
•
Filing: 1988-04-13
•
Granted: 1988-05-31
•
Expires: 2008-04-13
Abstract
Abstract A memory cell (10) has a bipolr decoupling element (56), (68), (82), (92) having an exterior contact (36). A refractory conductive layer (40) is formed on contact (36), and an initially nonconductive antifuse layer (48) is formed on refractory layer (40). A nonrefractory metal layer (50) is formed on the nonconductive layer (48). Blocking elements (56) (68), (82) (92) are connected to a word line (52), (78). When a specified voltage is impressed across the nonrefractory metal layer (50) and the word line (52), (78), nonrefractory metal diffuses through the initially nonconductive layer (48) to the refractory conductive layer (40) to provide a conductive path between the two.
Inventors
- 👤 Deems R. Hollingsworth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 08:34
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
154 words
An antifuse for a memory cell having at least two cell selection lines, comprising: a transistor decoupling element having a base, a collector, and a emitter comprising polysilicon; one of said selection lines being located over the base of said transistor and in electrical contact therewith; an initially nonconductive antifuse layer; a refractory conductive layer beneath said nonconductive antifuse layer; a silicide layer between said polysilicon of said emitter and said refractory conductive layer; a nonrefractory metal layer on said antifuse layer; said antifuse layer, said nonrefractory metal layer and said polysilicon of said emitter being in vertical alignment; said nonrefractory metal layer providing another cell selection lines; whereby metal from said nonrefractory metal layer diffuses through said antifuse layer to said refractory conductive layer upon application of a predetermined minimum potential between said nonrefractory layer and the base of said transistor to provide a conductive path between said nonrefractory layer and said emitter.
Claim 2
Dependent Claim
154 words
An antifuse for a memory cell having at least two cell selection lines, comprising: a transistor decoupling element having a base, a collector, and a emitter comprising polysilicon; one of said selection lines being located over the base of said transistor and in electrical contact therewith; an initially nonconductive antifuse layer; a refractory conductive layer beneath said nonconductive antifuse layer; a silicide layer between said polysilicon of said emitter and said refractory conductive layer; a nonrefractory metal layer on said antifuse layer; said antifuse layer, said nonrefractory metal layer and said polysilicon of said emitter being in vertical alignment; said nonrefractory metal layer providing another cell selection lines; whereby metal from said nonrefractory metal layer diffuses through said antifuse layer to said refractory conductive layer upon application of a predetermined minimum potential between said nonrefractory layer and the base of said transistor to provide a conductive path between said nonrefractory layer and said emitter.
Claim 3
Dependent Claim
15 words
The antifuse of claim 1, wherein said silicide layer on said emitter is platinum silicide.
Claim 4
Dependent Claim
15 words
The antifuse of claim 1 wherein said refractory conductive layer is a titanium tungsten alloy.
Claim 5
Dependent Claim
11 words
The antifuse of claim 1 wherein said nonrefractory metal is aluminum.
Claim 6
Dependent Claim
12 words
The antifuse of claim 1 wherein said antifuse is of amorphous silicon.
Claim 7
Dependent Claim
11 words
The antifuse of claim 5 wherein said amorphous silicon is undoped.
Claim 8
Dependent Claim
19 words
The antifuse of claim 6 wherein said antifuse layer has a thickness between about 500 Å and 3100 Å.
Claim 9
Dependent Claim
18 words
The antifuse of claim 1 wherein said predetermined minimum voltage is between about 4 to about 12 volts.
Claim 10
Dependent Claim
38 words
The antifuse of claim 1 further comprising a substrate in which at least the base and collector of said transistor are located, and a contact to the base of the transistor from a top surface of the substrate.
Claim 11
Dependent Claim
155 words
An antifuse product for a memory cell made by a process comprising the steps of: providing a semiconductor substrate; forming a bipolar transistor decoupling element at least partially in said substrate and having a base, a collector, and an emitter comprising at least a doped polysilicon portion; forming, in vertical alignment with said doped polysilicon portion, a silicide layer atop the doped polysilicon portion, a refractory conductive layer atop said silicide layer, and initially insulating antifuse layer atop said refractory conductive layer, and a nonrefractory metal layer atop said antifuse layer; providing cell selection lines one of which being located above the base of the transistor in electrical contact therewith, the other being provided by said nonrefractory metal layer; whereby metal from the nonrefractory metal layer migrates through the antifuse layer to the refractory layer to short the antifuse layer upon application of a predetermined electric potential between the nonrefractory layer and the polysilicon portion.
Claim 12
Dependent Claim
155 words
An antifuse product for a memory cell made by a process comprising the steps of: providing a semiconductor substrate; forming a bipolar transistor decoupling element at least partially in said substrate and having a base, a collector, and an emitter comprising at least a doped polysilicon portion; forming, in vertical alignment with said doped polysilicon portion, a silicide layer atop the doped polysilicon portion, a refractory conductive layer atop said silicide layer, and initially insulating antifuse layer atop said refractory conductive layer, and a nonrefractory metal layer atop said antifuse layer; providing cell selection lines one of which being located above the base of the transistor in electrical contact therewith, the other being provided by said nonrefractory metal layer; whereby metal from the nonrefractory metal layer migrates through the antifuse layer to the refractory layer to short the antifuse layer upon application of a predetermined electric potential between the nonrefractory layer and the polysilicon portion.
Claim 13
Dependent Claim
25 words
The antifuse product made by the process of claim 10 and further comprising annealing said doped polysilicon portion to diffuse dopant therefrom into said substrate.
Claim 14
Dependent Claim
21 words
The antifuse product made by the process of claim 10 and further comprising forming said nonrefractory metal layer substantially from aluminum.
Claim 15
Dependent Claim
20 words
The antifuse product made by the process of claim 10 and further comprising forming said antifuse layer of amorphous silicon.
Claim 16
Dependent Claim
37 words
The antifuse product made by the process of claim 10 and further comprising programming said antifuse by selectively applying a potential between said refractory metal layer and said polysilicon portion of between about four and twelve volts.
References Cited (Backward Citations)
US4146902A
Cited
JPS5720993A
Cited
US4424578A
Cited
US4499557A
Cited
US4471376A
Cited
US4441167A
Cited
US4569120A
Cited
US4569121A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-31 | 1991-11-30 | 1992-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-31 | 1995-11-30 | 1996-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-31 | 1999-11-30 | 2000-05-31 | $7700.00 | Window Closed / Lapsed |