Patent US5763898A successfully refreshed from Google Patents.
US5763898A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Above via metal-to-metal antifuses incorporating a tungsten via plug
Assignee: Microsemi SoC Corp
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Filing: 1996-10-03
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Granted: 1998-06-09
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Expires: 2016-10-03
Abstract
Abstract According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers. According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage. According to a third aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer disposed over a plug of an electrically conductive material disposed between two metallization layers.
Inventors
- 👤 Abdul R. Forouhi
- 👤 Frank W. Hawley
- 👤 John L. McCollum
- 👤 Yeouchung Yen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:48
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491; H10W20/01; H10W20/031; H10W20/064; H10W20/065; H10W20/41; H10W20/425
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
129 words
An electrically programmable antifuse disposed on an integrated circuit comprising: a first metalization layer disposed on an insulating portion of said integrated circuit; an interlayer dielectric layer disposed over said first metalization layer; a via having substantially parallel sidewalls completely penetrating said interlayer dielectric layer and exposing said first metalization layer; a layer of an electrically conductive material disposed in said via and in electrical contact with said first metalization layer, said electrically conductive material filling said via; a flat planar antifuse material layer disposed over said layer of electrically conductive material, said antifuse material layer including a layer of amorphous silicon sandwiched between a first and a second layer of an insulating material other than amorphous silicon; and a second metalization layer disposed over said antifuse material layer.
Claim 2
Dependent Claim
129 words
An electrically programmable antifuse disposed on an integrated circuit comprising: a first metalization layer disposed on an insulating portion of said integrated circuit; an interlayer dielectric layer disposed over said first metalization layer; a via having substantially parallel sidewalls completely penetrating said interlayer dielectric layer and exposing said first metalization layer; a layer of an electrically conductive material disposed in said via and in electrical contact with said first metalization layer, said electrically conductive material filling said via; a flat planar antifuse material layer disposed over said layer of electrically conductive material, said antifuse material layer including a layer of amorphous silicon sandwiched between a first and a second layer of an insulating material other than amorphous silicon; and a second metalization layer disposed over said antifuse material layer.
Claim 3
Dependent Claim
13 words
An antifuse according to claim 1 wherein said insulating material is silicon nitride.
Claim 4
Dependent Claim
17 words
An antifuse according to claim 2 further comprising an etch-stop/barrier layer disposed over said antifuse material layer.
Claim 5
Dependent Claim
39 words
An antifuse according to claim 3 wherein said etch-stop/barrier layer is fabricated of a material selected from the group consisting of: TiN, TiW, TiWN, W, TiC, WC and combinations of two or more of any of the foregoing materials.
Claim 6
Dependent Claim
155 words
An electrically programmable antifuse disposed on an integrated circuit comprising: a first metalization layer disposed on an insulating portion of said integrated circuit; an interlayer dielectric layer disposed over said first metalization layer; a via having substantially parallel sidewalls completely penetrating said interlayer dielectric layer and exposing said first metalization layer; a layer of an electrically conductive material disposed in said via and in electrical contact with said first metalization layer; an electrically conductive barrier layer disposed in said via over said layer of electrically conductive material, said electrically conductive barrier layer filling said via; a flat planar antifuse material layer disposed over said layer of electrically conductive material and in contact with said electrically conductive barrier layer, said antifuse material layer including a layer of amorphous silicon sandwiched between a first and a second layer of an insulating material other than amorphous silicon; and a second metalization layer disposed over said antifuse material layer.
Claim 7
Dependent Claim
155 words
An electrically programmable antifuse disposed on an integrated circuit comprising: a first metalization layer disposed on an insulating portion of said integrated circuit; an interlayer dielectric layer disposed over said first metalization layer; a via having substantially parallel sidewalls completely penetrating said interlayer dielectric layer and exposing said first metalization layer; a layer of an electrically conductive material disposed in said via and in electrical contact with said first metalization layer; an electrically conductive barrier layer disposed in said via over said layer of electrically conductive material, said electrically conductive barrier layer filling said via; a flat planar antifuse material layer disposed over said layer of electrically conductive material and in contact with said electrically conductive barrier layer, said antifuse material layer including a layer of amorphous silicon sandwiched between a first and a second layer of an insulating material other than amorphous silicon; and a second metalization layer disposed over said antifuse material layer.
Claim 8
Dependent Claim
13 words
An antifuse according to claim 5 wherein said insulating material is silicon nitride.
Claim 9
Dependent Claim
18 words
An antifuse according to claim 6 further comprising an etch- stop/barrier layer disposed over said antifuse material layer.
Claim 10
Dependent Claim
39 words
An antifuse according to claim 7 wherein said etch-stop/barrier layer is fabricated of a material selected from the group consisting of: TiN, TiW, TiWN, W, TiC, WC and combinations of two or more of any of the foregoing materials.
References Cited (Backward Citations)
US3634929A
Cited
US3675090A
Cited
US3717852A
Cited
US3877049A
Cited
US4271582A
Cited
US4322822A
Cited
US4455495A
Cited
US4261763A
Cited
US4357622A
Cited
US4565712A
Cited
US4323986A
Cited
US4424578A
Cited
US4499557A
Cited
US4420820A
Cited
US4361599A
Cited
US4441247A
Cited
US4585490A
Cited
EP0081226A3
Cited
US4507756A
Cited
US4507757A
Cited
EP0092871B1
Cited
US4489481A
Cited
US4590589A
Cited
US4617723A
Cited
US4569121A
Cited
US4569120A
Cited
US4847732A
Cited
US4628590A
Cited
US4535528A
Cited
US4796075A
Cited
EP0162529B1
Cited
US4651409A
Cited
US4602420A
Cited
US4751197A
Cited
US4912066A
Cited
US5087591A
Cited
US4748490A
Cited
US4949084A
Cited
EP0224418B1
Cited
US4647340A
Cited
US4899205A
Cited
US5266829A
Cited
US5134457A
Cited
US4823181A
Cited
US4943538A
Cited
US5166901A
Cited
US4876220A
Cited
US4881114A
Cited
US4893167A
Cited
US4916809A
Cited
US4740485A
Cited
US4907064A
Cited
US4732865A
Cited
US4792835A
Cited
US4795722A
Cited
US4981813A
Cited
US4796074A
Cited
US4800176A
Cited
EP0315421B1
Cited
EP0323078A3
Cited
US4822753A
Cited
US4882611A
Cited
US5210598A
Cited
DE3927033A1
Cited
US4937475B1
Cited
US4937475A
Cited
US5093711A
Cited
US4920072A
Cited
US4910418A
Cited
US4933898A
Cited
US5010039A
Cited
US4914055A
Cited
EP0671767A3
Cited
EP0414361A3
Cited
EP0416903A3
Cited
US5021849A
Cited
EP0436387A3
Cited
US5272369A
Cited
US5070384A
Cited
EP0452091B1
Cited
US5181096A
Cited
US5272101A
Cited
EP0455414A1
Cited
US5061646A
Cited
US5059555A
Cited
US5106773A
Cited
US5095362A
Cited
US5087958A
Cited
US5493147A
Cited
US5163180A
Cited
EP0501120A3
Cited
US5166556A
Cited
EP0500034A1
Cited
US5100827A
Cited
EP0501687A3
Cited
US5121184A
Cited
US5322812A
Cited
US5196724A
Cited
US5319238A
Cited
US5557136A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-08 | 2001-12-08 | 2002-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-08 | 2005-12-08 | 2006-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-08 | 2009-12-08 | 2010-06-09 | $7700.00 | Window Closed / Lapsed |