US5557136A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable interconnect structures and programmable integrated circuits
Assignee: QuickLogic Corp
•
Filing: 1992-06-01
•
Granted: 1996-09-17
•
Expires: 2012-06-01
Abstract
Abstract Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.
Inventors
- 👤 Kathryn E. Gordon
- 👤 Richard J. Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:48
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
103 words
A field programmable gate array comprising: a first metal conductor; an insulating layer overlaying the first metal conductor, the insulating layer having an opening formed therein; a plug in the opening, the plug comprising tungsten, the plug contacting the first conductor, a top surface of the insulating layer having a portion adjacent the plug, the portion being substantially coplanar with a top surface of the plug; amorphous silicon having a substantially planar bottom surface which overlays and contacts the plug and also overlays and contacts the adjacent portion of the insulating layer; and a second metal conductor overlaying and contacting the amorphous silicon.
Claim 2
Dependent Claim
103 words
A field programmable gate array comprising: a first metal conductor; an insulating layer overlaying the first metal conductor, the insulating layer having an opening formed therein; a plug in the opening, the plug comprising tungsten, the plug contacting the first conductor, a top surface of the insulating layer having a portion adjacent the plug, the portion being substantially coplanar with a top surface of the plug; amorphous silicon having a substantially planar bottom surface which overlays and contacts the plug and also overlays and contacts the adjacent portion of the insulating layer; and a second metal conductor overlaying and contacting the amorphous silicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-17 | 2000-03-18 | 2000-09-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-17 | 2004-03-18 | 2004-09-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-17 | 2008-03-18 | 2008-09-17 | $7700.00 | Window Closed / Lapsed |