Programmable interconnect architecture

Claim 2

In an integrated circuit, a programmable interconnect architecture, including: a plurality of wiring channels, running in a selected direction each of said wiring channels including a plurality of wiring segments, a plurality of electrically programmable elements, each having an unprogrammed non-conductive state and a programmed conductive state, said electrically programmable elements connected between adjacent ones of said wiring segments in said wiring channels, a plurality of programming lines, each of said programming lines associated with corresponding ones of said wiring segments in said plurality of wiring channels, a plurality of sets of programming transistors, each of said sets including a programming transistor connected between one of said programming lines and one of said corresponding ones of said wiring segments, each of said programming transistors having a control element, a plurality of control lines, each of said control lines connected to the control elements of the ones of said programming transistors connected to wiring segments in the same wiring channel.

Claim 3

The programmable interconnect architecture of claim 1, further including: programming means, responsive to control signals from input/output pins on said integrated circuit, for selectively applying programming voltages to said control lines.

Claim 4

In an integrated circuit, a programmable interconnect architecture, including: a plurality of wiring channels, running in a selected direction, each of said wiring channels including a plurality of wiring segments, a plurality of electrically programmable elements, each having an unprogrammed non-conductive state and a programmed conductive state, said electrically programmable elements connected between adjacent ones of said wiring segments in said wiring channels, a plurality of programming lines, each of said programming lines associated with ones of said wiring segments, a plurality of programming transistors, each of said programming transistors connected between one of said programming lines and the one of said wiring segments associated therewith, each of said programming transistors having a control element, a control line connected to the control elements of said programming transistors.

Claim 5

In an integrated circuit, a programmable interconnect architecture, including: a plurality of wiring channels, running in a selected direction, each of said wiring channels including a plurality of wiring segments, a plurality of electrically programmable elements, each having an unprogrammed non-conductive state and a programmed conductive state, said electrically programmable elements connected between adjacent ones of said wiring segments in said wiring channels, a plurality of programming lines, each of said programming lines associated with ones of said wiring segments, a plurality of programming transistors, each of said programming transistors connected between one of said programming lines and the one of said wiring segments associated therewith, each of said programming transistors having a control element, a control line connected to the control elements of said programming transistors.

Claim 6

The programmable interconnect architecture of claim 3, further including: programming means, responsive to control signals from input/output pins on said integrated circuit, for selectively applying programming voltages to said control line.

Claim 7

In an integrated circuit, a programmable interconnect architecture including: a plurality of wiring channels, running in a selected direction, each of said wiring channels including a plurality of wiring segments, a plurality of electrically programmable elements, each having an unprogrammed non-conductive state and a programmed conductive state, said electrically programmable elements connected between adjacent ones of said wiring segments in said wiring channels, a programming line associated with said wiring channels, a plurality of sets of programming transistors, each of said sets including at least two programming transistors connected in series between said programming line and one of said wiring segments, each of said programming transistors having a control element, a plurality of control lines associated with said programming transistors, said control lines connected to the control elements of selected ones of said programming transistors such that activation of selected ones of said control lines turns on all of said programming transistors in only a selected one of said sets.

Claim 8

In an integrated circuit, a programmable interconnect architecture including: a plurality of wiring channels, running in a selected direction, each of said wiring channels including a plurality of wiring segments, a plurality of electrically programmable elements, each having an unprogrammed non-conductive state and a programmed conductive state, said electrically programmable elements connected between adjacent ones of said wiring segments in said wiring channels, a programming line associated with said wiring channels, a plurality of sets of programming transistors, each of said sets including at least two programming transistors connected in series between said programming line and one of said wiring segments, each of said programming transistors having a control element, a plurality of control lines associated with said programming transistors, said control lines connected to the control elements of selected ones of said programming transistors such that activation of selected ones of said control lines turns on all of said programming transistors in only a selected one of said sets.

Claim 9

The programmable interconnect architecture of claim 5, further including: programming means, responsive to control signals from input/output pins on said integrated circuit, for selectively applying programming voltages to said control lines.

Claim 10

A programmable interconnect architecture for integrated circuits, including: a plurality of wiring channels, running in a selected direction each of said wiring channels including a plurality of wiring segments, a plurality of electrically programmable elements, each having an unprogrammed non-conductive state and a programmed conductive state, said electrically programmable elements connected between adjacent ones of said wiring segments in said wiring channels, a series-pass transistor connected across each of said electrically-programmable elements, each of said series-pass transistors having a control element, the control elements of the ones of said series-pass transistors in corresponding positions along said wiring channels being commonly connected to one of a set of first control lines, first and second programming transistors, associated with each of said wiring segments, connected in series between the one of said wiring segments with which they are associated and a fixed voltage potential, said first programming transistor connected to the one of said wiring segments with which it is associated and said second programming transistor connected to said fixed voltage potential, said first and second programming transistors each having a control element, a set of second control lines, each of said second control lines associated with the ones of said wiring segments in corresponding positions in their respective wiring channels, each of said control lines connected to the control elements of the ones of said first programming transistors associated with said wiring segments in corresponding positions in their respective wiring channels, the control element of each of said second programming transistors being connected to the wiring segment adjacent in a selected direction to the wiring segment with which said programming transistor is associated.

Claim 11

A programmable interconnect architecture for integrated circuits, including: a plurality of wiring channels, running in a selected direction each of said wiring channels including a plurality of wiring segments, a plurality of electrically programmable elements, each having an unprogrammed non-conductive state and a programmed conductive state, said electrically programmable elements connected between adjacent ones of said wiring segments in said wiring channels, a series-pass transistor connected across each of said electrically-programmable elements, each of said series-pass transistors having a control element, the control elements of the ones of said series-pass transistors in corresponding positions along said wiring channels being commonly connected to one of a set of first control lines, first and second programming transistors, associated with each of said wiring segments, connected in series between the one of said wiring segments with which they are associated and a fixed voltage potential, said first programming transistor connected to the one of said wiring segments with which it is associated and said second programming transistor connected to said fixed voltage potential, said first and second programming transistors each having a control element, a set of second control lines, each of said second control lines associated with the ones of said wiring segments in corresponding positions in their respective wiring channels, each of said control lines connected to the control elements of the ones of said first programming transistors associated with said wiring segments in corresponding positions in their respective wiring channels, the control element of each of said second programming transistors being connected to the wiring segment adjacent in a selected direction to the wiring segment with which said programming transistor is associated.

Claim 12

The programmable interconnect architecture of claim 7, further including programming means, responsive to said control means, for applying programming voltages to selected ones of said wiring segments.

Claim 13

A programmable interconnect architecture for integrated circuits, including: a plurality of wiring channels, running in a selected direction, each of said wiring channels including a plurality of wiring segments, a plurality of electrically programmable elements, each having an unprogrammed non-conductive state and a programmed conductive state, said electrically programmable elements connected between adjacent ones of said wiring segments in said wiring channels, series-pass transistors connected across selected ones of said programmable elements, each of said series-pass transistors having a control element, control means, responsive to signals appearing on input/output terminals of said integrated circuit, for selectively activating said control elements of said series-pass transistors.

Claim 14

A programmable interconnect architecture for integrated circuits, including: a plurality of wiring channels, running in a selected direction, each of said wiring channels including a plurality of wiring segments, a plurality of electrically programmable elements, each having an unprogrammed non-conductive state and a programmed conductive state, said electrically programmable elements connected between adjacent ones of said wiring segments in said wiring channels, series-pass transistors connected across selected ones of said programmable elements, each of said series-pass transistors having a control element, control means, responsive to signals appearing on input/output terminals of said integrated circuit, for selectively activating said control elements of said series-pass transistors.

Claim 15

In an integrated circuit, an electrically-programmable interconnect architecture, including: a plurality of function modules placed in an array, each of said modules having input and output nodes, addressing means for selecting a unique one of said modules, a plurality of first sets of wiring channels in said array, at least some of said sets of wiring channels having at least one wiring channel comprising at least two wiring segments and wherein each of said input and output nodes is electrically connected to a different segment in a different channel in one of said first sets said wiring channels, isolation means, connected between said input and output nodes and said first ones of said wiring segments, for selectively breaking the electrical connection between said nodes and said wiring segments, output node driving means, co-operating with said isolation means for placing the output node of a selected one of said modules at a first predetermined voltage if said module has been selected by said addressing means and at a second predetermined voltage of said module has not been selected by said addressing means, a plurality of output node wiring segments, each module having an electrically-programmable element connected between its output code and a selected one of said output nod wiring segments, a plurality of second sets of wiring channels, each of said second sets including at least one wiring segment forming an intersection with at least one wiring segment forming an intersection with at least one of said output node wiring segments, and an electrically programmable element, having an unprogrammed non-conductive state and a programmed conductive state, connected across at least one of said intersections.

Claim 16

In an integrated circuit, an electrically-programmable interconnect architecture, including: a plurality of function modules placed in an array, each of said modules having input and output nodes, addressing means for selecting a unique one of said modules, a plurality of first sets of wiring channels in said array, at least some of said sets of wiring channels having at least one wiring channel comprising at least two wiring segments and wherein each of said input and output nodes is electrically connected to a different segment in a different channel in one of said first sets said wiring channels, isolation means, connected between said input and output nodes and said first ones of said wiring segments, for selectively breaking the electrical connection between said nodes and said wiring segments, output node driving means, co-operating with said isolation means for placing the output node of a selected one of said modules at a first predetermined voltage if said module has been selected by said addressing means and at a second predetermined voltage of said module has not been selected by said addressing means, a plurality of output node wiring segments, each module having an electrically-programmable element connected between its output code and a selected one of said output nod wiring segments, a plurality of second sets of wiring channels, each of said second sets including at least one wiring segment forming an intersection with at least one wiring segment forming an intersection with at least one of said output node wiring segments, and an electrically programmable element, having an unprogrammed non-conductive state and a programmed conductive state, connected across at least one of said intersections.

Claim 17

In a programmable integrated circuit array of functional devices having inputs and outputs programmably connectable to plural interconnect conductors which are segmented into discrete lengths, apparatus including: a permanent irreversibly programmable first circuit connection device serially connected between at least one pair of said discrete lengths of segmented conductors, and a temporary reversibly programmable second circuit connection device connected in parallel across said first circuit connection device.

Claim 18

In a programmable integrated circuit array of functional devices having inputs and outputs programmably connectable to plural interconnect conductors which are segmented into discrete lengths, apparatus including: a permanent irreversibly programmable first circuit connection device serially connected between at least one pair of said discrete lengths of segmented conductors, and a temporary reversibly programmable second circuit connection device connected in parallel across said first circuit connection device.

Claim 19

The apparatus of claim 11 wherein said second circuit connection device is a transistor.