US4749947A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Grid-based, "cross-check" test structure for testing integrated circuits
Assignee: Duet Technologies Inc
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Filing: 1986-03-10
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Granted: 1988-06-07
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Expires: 2006-03-10
Abstract
Abstract A new test structure is described which allows full testing of highly complex Integrated Circuits. The test structure consists of a grid of externally as well as individually accessible probe-lines and sense-lines with electronic switches at the crossings of said probe and the sense-lines. One end of the switches is tied to an array of test-points on the IC that are to be either monitored or controlled during the testing, and the other end of the switches is tied to a sense-line. The ON and the OFF states of the switches are controlled by probe-lines. The probe and sense lines are connected to test electronics, thus permitting the test electronics to control the electrical signals on the probe-lines and to measure or apply signals on the sense-lines. Thus, by the excitation of an appropriate probe-line and the monitoring of an appropriate sense-line, the test signals present at any one of the test-points can be measured. Conversly, by the excitation of an appropriate probe-line and application of a test signal on another appropriate sense-line the electrical signal on any of the test-points can be externally controlled for the purpose of testing.
Inventors
- 👤 Tushar R. Gheewala
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 05:13
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07392
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
191 words
An apparatus for electrically testing an integrated circuit comprising: a plurality of electronic switches incorporated into said integrated circuit to be tested; an array of test-points forming a grid structure; a plurality of probe-lines for introducing signals; a plurality of sense-lines at least for sensing signals; each one of said electronic switches having a test terminal, a control terminal and a sense terminal, said test terminal being electrically connected to a single one of said test-points at a selected location of an arbitrary function combinatorial logic gate in said integrated circuit, said locations including an input pad, an output pad, a power supply terminal or a clock distribution point, said sense terminal being connected to a single one of said sense-lines, and said control terminal being connected to a single one of said probe-lines; test electronics coupled to said probe-lines and to said sense-lines for applying to selected ones of said probe-lines selected ON signals to enable selected ones of said electronic switches to generate test signals on said sense-lines for analysis; and means coupled to said sense-lines for observing individual test signals associated with single one of said electronic switches.
Claim 2
Independent Claim
191 words
An apparatus for electrically testing an integrated circuit comprising: a plurality of electronic switches incorporated into said integrated circuit to be tested; an array of test-points forming a grid structure; a plurality of probe-lines for introducing signals; a plurality of sense-lines at least for sensing signals; each one of said electronic switches having a test terminal, a control terminal and a sense terminal, said test terminal being electrically connected to a single one of said test-points at a selected location of an arbitrary function combinatorial logic gate in said integrated circuit, said locations including an input pad, an output pad, a power supply terminal or a clock distribution point, said sense terminal being connected to a single one of said sense-lines, and said control terminal being connected to a single one of said probe-lines; test electronics coupled to said probe-lines and to said sense-lines for applying to selected ones of said probe-lines selected ON signals to enable selected ones of said electronic switches to generate test signals on said sense-lines for analysis; and means coupled to said sense-lines for observing individual test signals associated with single one of said electronic switches.
Claim 3
Dependent Claim
32 words
The apparatus according to claim 1 wherein said test electronics further comprises means incorporated into said integrated circuit for storing representations of said test signals generated on said sense-lines in compacted form.
Claim 4
Dependent Claim
55 words
The apparatus according to claim 1 wherein said electronic switch comprises a Field Effect Transistor (FET) having as said control terminal a gate electrode, as said test terminal a first one of a source electrode and a drain electrode, and as said sense terminal a second one of said source electrode and said drain electrode.
Claim 5
Dependent Claim
62 words
The apparatus according to claim 3 wherein said gate electrode is coupled to said probe line, and a first one of said source electrode and said drain electrode is connected to one of said sense-lines and a second one of said source electrode and said drain electrode is connected to said test-point, such thatcsaid gate electrode is never connected to a test-point.
Claim 6
Dependent Claim
50 words
The apparatus according to claim 1 wherein each one of said electronic switches is an electronic logic gate, said probe-lines and said test-points on said integrated circuit providing input signals to each said logic gate, and wherein output signals of each said logic gate is electrically connected to said sense-lines.
Claim 7
Dependent Claim
29 words
The apparatus according to claim 1, 4 or 5 wherein said probe-lines are parallel to each other and orthogonal to said sense-lines, said sense-lines being parallel to each other.
Claim 8
Dependent Claim
23 words
The apparatus according to claim 1 further including means coupled to said sense-lines for introducing control signals to selected ones of said sense-lines.
Claim 9
Dependent Claim
15 words
The apparatus according to claim 1 wherein said array is a three-dimensional array of test-points.
Claim 10
Dependent Claim
29 words
The apparatus according to claim 1 wherein said observing means comprise beams of either electrons or coherent radiation for communication with said test electronics external of said integrated circuit.
Claim 11
Dependent Claim
25 words
The apparatus according to claim 1 wherein said observing means comprise means coupled to kerf areas between adjacent integrated circuit devices on a semiconductor wafer.
Claim 12
Dependent Claim
30 words
The apparatus according to claim 1 wherein said observing means comprise means coupled to primary input pads and primary output pads of adjacent integrated circuit devices on a semiconductor wafer.
Claim 13
Dependent Claim
18 words
The apparatus according to claim 1 wherein said sense-lines are further for introducing electrical signals at said test-points.
Claim 14
Dependent Claim
33 words
The apparatus according to claim 1 further including interconnection means for coupling sense-lines or probe-lines between a plurality of said integrated circuits for coupling said plurality of integrated circuits to said test electronics.
Claim 15
Dependent Claim
22 words
The apparatus according to claim 1 wherein said test electronics are incorporated into a circuit on a wafer containing said integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-07 | 1991-12-07 | 1992-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-07 | 1995-12-07 | 1996-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-07 | 1999-12-07 | 2000-06-07 | $7700.00 | Window Closed / Lapsed |