US4293919A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Level sensitive scan design (LSSD) system
Assignee: International Business Machines Corp
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Filing: 1979-08-13
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Granted: 1981-10-06
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Expires: 1999-08-13
Abstract
Abstract One of the significant features of the invention, as in U.S. Pat. No. 3,783,254, is the implementation of shift register latches as basic building blocks in a logic organization and system with combinational logic networks which provide the excitation for the shift register latches. These shift register latches in the invention as well as in the patent contain a pair of latches where one is a "master" latch and another a "slave". The structure in the patent requires the "master" and "slave" latches to be part of the shift register for scan-in/scan-out. However, only the "master" may be set with data from the logic system surrounding it while the "slave" may only be set with data which previously resided in the related "master" latch. Thus, in those logic organizations where only the "master" latch output is required, the usefulness of the "slave" latch is limited to scan-in/scan-out. In the shift register latch of the invention, the "slave" latch must be set with the data that resided in the related "master" latch during scan-in/scan-out. However, in logic systems requiring the use of only one latch of the shift register latch, both "master" and "slave" latches can perform independent of the other; that is, each latch may be set with data from the logic system without any influence from the other latch in the same shift register latch. Similarly, both "master" and "slave" may feed different sections of the logic surrounding it.
Inventors
- 👤 Sumit Dasgupta
- 👤 Prabhakar Goel
- 👤 Thomas W. Williams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:23
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541; G01R31/318583
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
123 words
A system of logic for performing at least one predetermined logical function, said system of logic including: a plurality of combinational logic circuits; a multi-stage shift register having an input, an output, and shift controls; each stage of said multi-stage shift register comprising first and second interconnected DC latches; and circuit means interconnecting said plurality of combinational logic circuits and said first and second interconnected D.C. latches of said multi-stage shift register, whereby said shift register is available for use in the testing of each of said plurality of combinational logic circuits and each of said D.C. latches of said multi-stage shift register is also available for use as an independently operable data latch in providing said at least one predetermined logical function.
Claim 2
Independent Claim
123 words
A system of logic for performing at least one predetermined logical function, said system of logic including: a plurality of combinational logic circuits; a multi-stage shift register having an input, an output, and shift controls; each stage of said multi-stage shift register comprising first and second interconnected DC latches; and circuit means interconnecting said plurality of combinational logic circuits and said first and second interconnected D.C. latches of said multi-stage shift register, whereby said shift register is available for use in the testing of each of said plurality of combinational logic circuits and each of said D.C. latches of said multi-stage shift register is also available for use as an independently operable data latch in providing said at least one predetermined logical function.
Claim 3
Dependent Claim
586 words
A system of logic for performing at least one predetermined logical function, as recited in claim 1 further characterized in that at least certain of said D.C. latches of said multi-stage shift register are comprised of the following circuitry (FIG. 9B): first, second, third, fourth, seventh, eighth, ninth and tenth AND-INVERT circuits each having first and second inputs and an output; fifth, sixth, eleventh and twelfth AND-INVERT circuits each having first, second and third inputs and an output; a first inverter circuit (41) having its input connected to said first input of said first AND-INVERT circuit (39) and its output connected to said first input of said second AND-INVERT (40) circuit; a second inverter circuit having its input connected to said first input of said third AND-INVERT circuit and its output connected to said first input of said fourth AND-INVERT circuit; a third inverter circuit (47) having its input connected to the first input of said ninth AND-INVERT circuit (45) and its output connected to said first input of said tenth AND-INVERT circuit (46); an input U connected to said first input of said first AND-INVERT circuit (39); a clock source A connected in common to said second inputs of said first and second AND-INVERT circuit (39, 49); an input E1 connected to said first input of said third AND-INVERT circuit; a clock source C1 connected in common to said second inputs of said third and fourth AND-INVERT CIRCUITS: an input E2 connected to said first input of said ninth AND-INVERT circuit; a clock source C2 connected in common to said second input of said ninth and tenth AND-INVERT circuits (45, 46); a direct connection between said output of said first AND-INVERT circuit (39) and said first input of said fifth AND-INVERT circuit; a direct connection between said output of said third AND-INVERT circuit and said second input of said fifth AND-INVERT circuit; a direct connection between said output of said fourth AND-INVERT circuit and said second input of said sixth AND-INVERT circuit; a direct connection between said output of said second AND-INVERT circuit (40) and said third input of said sixth AND-INVERT circuit; an output terminal L connected to said output of said fifth AND-INVERT circuit; a direct connection connecting in common said output of said fifth AND-INVERT circuit, said first input of said sixth AND-INVERT circuit and said first input of said seventh AND-INVERT circuit (43); a direct connection connecting in common said output of said sixth AND-INVERT circuit, said third input of said fifth AND-INVERT circuit and said first input of said eighth AND-INVERT circuit (44); a clock source B connected in common to said second inputs of said seventh and eighth AND-INVERT circuit (43, 44); a direct connection between said output of said seventh AND-INVERT circuit (43) and said first input of said eleventh AND-INVERT circuit; a direct connection between said output of said ninth AND-INVERT circuit (45) and said second input of said eleventh AND-INVERT circuit; a direct connection between said output of said eighth AND-INVERT circuit (44) and said third input of said twelfth AND-INVERT circuit; a direct connection between said output of said tenth AND-INVERT circuit (46) and said second input of said twelth AND-INVERT circuit; a direct connection between said output of said eleventh AND-INVERT circuit and said first input of said twelfth AND-INVERT circuit; a direct connection between said output of said twelfth AND-INVERT circuit and said third input of said eleventh AND-INVERT circuit; and, an output V connected to said output of said eleventh AND-INVERT circuit.
Claim 4
Dependent Claim
571 words
A multi-stage shift register characterized in that at least certain of said stages of said multi-stage shift register are comprised of the following circuitry (FIG. 9B): first, second, third, fourth, seventh, eighth, ninth and tenth AND-INVERT circuits each having first and second inputs and an output; fifth, sixth, eleventh and twelfth AND-INVERT circuits each having first, second and third inputs and an output; a first inverter circuit (41) having its input connected to said first input of said first AND-INVERT circuit (39) and its output connected to said first input of said second AND-INVERT (40) circuit; a second inverter circuit having its input connected to said first input of said third AND-INVERT circuit and its output connected to said first input of said fourth AND-INVERT circuit; a third inverter circuit (47) having its input connected to the first input of said ninth AND-INVERT circuit (45) and its output connected to said first input of said tenth AND-INVERT circuit (46); an input U connected to said first input of said first AND-INVERT circuit (39); a clock source A connected in common to said second inputs of said first and second AND-INVERT circuit (39, 40); an input E1 connected to said first input of said third AND-INVERT circuit; a clock source C1 connected in common to said second inputs of said third and fourth AND-INVERT CIRCUITS: an input E2 connected to said first input of said ninth AND-INVERT circuit; a clock source C2 connected in common to said second input of said ninth and tenth AND-INVERT circuits (45, 46); a direct connection between said output of said first AND-INVERT circuit (39) and said first input of said fifth AND-INVERT circuit; a direct connection between said output of said third AND-INVERT circuit and said second input of said fifth AND-INVERT circuit; a direct connection between said output of said fourth AND-INVERT circuit and said second input of said sixth AND-INVERT circuit; a direct connection between said output of said second AND-INVERT circuit (40) and said third input of said sixth AND-INVERT circuit; an output terminal L connected to said output of said fifth AND-INVERT circuit; a direct connection connecting in common said output of said fifth AND-INVERT circuit, said first input of said sixth AND-INVERT circuit and said first input of said seventh AND-INVERT circuit (43); a direct connection connecting in common said output of said sixth AND-INVERT circuit, said third input of said fifth AND-INVERT circuit and said first input of said eighth AND-INVERT circuit (44); a clock source B connected in common to said second inputs of said seventh and eighth AND-INVERT circuit (43, 44); a direct connection between said output of said seventh AND-INVERT circuit (43) and said first input of said eleventh AND-INVERT circuit; a direct connection between said output of said ninth AND-INVERT circuit (45) and said second input of said eleventh AND-INVERT circuit; a direct connection between said output of said eighth AND-INVERT circuit (44) and said third input of said twelfth AND-INVERT circuit; a direct connection between said output of said tenth AND-INVERT circuit (46) and said second input of said twelfth AND-INVERT circuit; a direct connection between said output of said eleventh AND-INVERT circuit and said first input of said twelfth AND-INVERT circuit; a direct connection between said output of said twelfth AND-INVERT circuit and said third input of said eleventh AND-INVERT circuit; and, an output V connected to said output of said eleventh AND-INVERT circuit.
Claim 5
Dependent Claim
571 words
A multi-stage shift register characterized in that at least certain of said stages of said multi-stage shift register are comprised of the following circuitry (FIG. 9B): first, second, third, fourth, seventh, eighth, ninth and tenth AND-INVERT circuits each having first and second inputs and an output; fifth, sixth, eleventh and twelfth AND-INVERT circuits each having first, second and third inputs and an output; a first inverter circuit (41) having its input connected to said first input of said first AND-INVERT circuit (39) and its output connected to said first input of said second AND-INVERT (40) circuit; a second inverter circuit having its input connected to said first input of said third AND-INVERT circuit and its output connected to said first input of said fourth AND-INVERT circuit; a third inverter circuit (47) having its input connected to the first input of said ninth AND-INVERT circuit (45) and its output connected to said first input of said tenth AND-INVERT circuit (46); an input U connected to said first input of said first AND-INVERT circuit (39); a clock source A connected in common to said second inputs of said first and second AND-INVERT circuit (39, 40); an input E1 connected to said first input of said third AND-INVERT circuit; a clock source C1 connected in common to said second inputs of said third and fourth AND-INVERT CIRCUITS: an input E2 connected to said first input of said ninth AND-INVERT circuit; a clock source C2 connected in common to said second input of said ninth and tenth AND-INVERT circuits (45, 46); a direct connection between said output of said first AND-INVERT circuit (39) and said first input of said fifth AND-INVERT circuit; a direct connection between said output of said third AND-INVERT circuit and said second input of said fifth AND-INVERT circuit; a direct connection between said output of said fourth AND-INVERT circuit and said second input of said sixth AND-INVERT circuit; a direct connection between said output of said second AND-INVERT circuit (40) and said third input of said sixth AND-INVERT circuit; an output terminal L connected to said output of said fifth AND-INVERT circuit; a direct connection connecting in common said output of said fifth AND-INVERT circuit, said first input of said sixth AND-INVERT circuit and said first input of said seventh AND-INVERT circuit (43); a direct connection connecting in common said output of said sixth AND-INVERT circuit, said third input of said fifth AND-INVERT circuit and said first input of said eighth AND-INVERT circuit (44); a clock source B connected in common to said second inputs of said seventh and eighth AND-INVERT circuit (43, 44); a direct connection between said output of said seventh AND-INVERT circuit (43) and said first input of said eleventh AND-INVERT circuit; a direct connection between said output of said ninth AND-INVERT circuit (45) and said second input of said eleventh AND-INVERT circuit; a direct connection between said output of said eighth AND-INVERT circuit (44) and said third input of said twelfth AND-INVERT circuit; a direct connection between said output of said tenth AND-INVERT circuit (46) and said second input of said twelfth AND-INVERT circuit; a direct connection between said output of said eleventh AND-INVERT circuit and said first input of said twelfth AND-INVERT circuit; a direct connection between said output of said twelfth AND-INVERT circuit and said third input of said eleventh AND-INVERT circuit; and, an output V connected to said output of said eleventh AND-INVERT circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-05 | 1985-04-06 | 1985-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-05 | 1989-04-06 | 1989-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-05 | 1993-04-06 | 1993-10-06 | $7700.00 | Window Closed / Lapsed |