US3795859A
Expired / Lapsed
US
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Method and apparatus for determining the electrical characteristics of a memory cell having field effect transistors
Assignee: International Business Machines Corp
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Filing: 1972-07-03
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Granted: 1974-03-05
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Expires: 1992-07-03
Abstract
Abstract The electrical characteristics of a field effect transistor (FET) of a memory cell connected to a ZERO bit line and of an FET of the memory cell connected to a ONE bit line are determined through applying a substantially constant voltage to one of the ZERO and ONE bit lines while changing the voltage condition on the other of the bit lines. In one embodiment, the FET is a load device of the memory cell and has its source electrode connected to one of the bit lines and also to the drain electrode of another FET, which has its gate electrode connected to the other of the bit lines and functions as an active device of the cell. A substantially constant voltage is applied to the gate electrode through one of the bit lines to inactivate the FET which has its drain electrode connected to the source electrode of the FET having its electrical characteristics determined. The other of the bit lines is discharged for a predetermined period of time and then allowed to charge for another predetermined period of time. The measurement of this charged voltage will indicate whether the FET, which is the load device, is connected to the bit line and has the desired gain and whether the leakage current through the bit line is too high. In the other embodiment, a substantially constant voltage is applied to an FET which is the active device and has its drain electrode connected to one of the bit lines to have a substantially constant voltage applied thereto while its gate electrode is connected to the other of the bit lines to have two different voltages applied thereto. The difference in current flow through the active FET having the two different voltages applied to its gate electrode is employed to determine the threshold voltage of the FET.
Inventors
- 👤 J Benante
- 👤 N Donofrio
- 👤 R Linton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:08
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/26; G01R31/27; G01R31/275; G11; G11C; G11C29/00; G11C29/04; G11C29/50; G06; G06F; G06F2201/00; G06F2201/81; G11C2029/5004; G11C2029/5006
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
141 words
A method for determining electrical characteristics of a memory cell including a first field effect transistor having one of its electrodes connected to a ZERO bit line and a second field effect transistor having one of its electrodes connected to a ONE bit line including: applying a substantially constant voltage to one of the ZERO and ONE bit lines while changing the voltage condition on the other of the ZERO and ONE bit lines and determining whether one of the first and second field effect transistors has a desired electrical characteristic; and then applying the substantially constant voltage to the other of the ZERO and ONE bit lines while changing the voltage condition on the one of the ZERO and ONE bit lines and determining whether the other of the first and second field effect transistors has a desired electrical characteristic.
Claim 2
Independent Claim
141 words
A method for determining electrical characteristics of a memory cell including a first field effect transistor having one of its electrodes connected to a ZERO bit line and a second field effect transistor having one of its electrodes connected to a ONE bit line including: applying a substantially constant voltage to one of the ZERO and ONE bit lines while changing the voltage condition on the other of the ZERO and ONE bit lines and determining whether one of the first and second field effect transistors has a desired electrical characteristic; and then applying the substantially constant voltage to the other of the ZERO and ONE bit lines while changing the voltage condition on the one of the ZERO and ONE bit lines and determining whether the other of the first and second field effect transistors has a desired electrical characteristic.
Claim 3
Dependent Claim
126 words
The method according to claim 1 in which the first field effect transistor has its drain electrode connected to the ZERO bit line and its gate electrode connected to the ONE bit line and the second field effect transistor has its drain electrode connected to the ONE bit line and its gate electrode connected to the ZERO bit line including: applying the substantially constant voltage to the drain electrode of the field effect transistor having its electrical characteristic determined; changing the voltage condition on the gate electrode of the same field effect transistor having its electrical characteristic determined; and determining the threshold voltage of the field effect transistor by determining the current flow through the field effect transistor at different voltages applied to its gate electrode.
Claim 4
Dependent Claim
251 words
The method according to claim 1 in which the first field effect transistor has its source electrode connected to the ZERO bit line and its drain and gate electrodes connected to a common voltage source with its source electrode also connected to the drain electrode of a third field effect transistor having its gate electrode connected to the ONE bit line and the second field effect transistor has its source electrode connected to the ONE bit line and its drain and gate electrodes connected to a common voltage source with its source electrode also connected to the drain electrode of a fourth field effect transistor having its gate electrode connected to the ZERO bit line including: applying the substantially constant voltage to the gate electrode of one of the third and fourth field effect transistors having its drain electrode connected to the source electrode of the field effect transistor having its electrical characteristic determined while changing the voltage condition on the source electrode of the field effect transistor having its electrical characteristic determined by discharging for a first predetermined period of time the bit line to which the source electrode of the field effect transistor having its electrical characteristic determined is connected and then allowing the bit line to charge for a second predetermined period of time; and determining the electrical characteristic of the field effect transistor by determining if the charged voltagE on the bit line reaches a predetermined value at the end of the second predetermined period of time.
Claim 5
Dependent Claim
93 words
The method according to claim 3 in which the electrical characteristics determined of each of the first and second field effect transistors includes whether the field effect transistor is connected to the bit line, the gain of the field effect transistor, and the leakage current from the junction of the source electrode of the field effect transistor and the drain electrode of the field effect transistor of the third and fourth field effect transistors along the bit line connected to the source electrode of the field effect transistor having its electrical characteristics determined.
Claim 6
Independent Claim
210 words
An apparatus for determining electrical characteristics of a memory cell including a first field effect transistor having one of its electrodes connected to a ZERO bit line and a second field effect transistor having one of its electrodes connected to a ONE bit line, said apparatus including: first means to apply a substantially constant voltage selectively to each of the ZERO and ONE bit lines; 9 second means to change the voltage condition on the other of the ZERO and ONE bit lines from that to which said first means is applying the substantially constant voltage; and third means to determine whether one of the first and second field effect transistors has a desired electrical characteristic when said first means is applying the substantially constant voltage to one of the ZERO and ONE bit lines and said second means is changing the voltage condition on the other of the ZERO and ONE bit lines and whether the other of the first and second field effect transistors has a desired electrical characteristic when said first means is applying the substantially constant voltage to the other of the ZERO and ONE bit lines and said second means is changing the voltage condition on the one of the ZERO and ONE bit lines.
Claim 7
Independent Claim
210 words
An apparatus for determining electrical characteristics of a memory cell including a first field effect transistor having one of its electrodes connected to a ZERO bit line and a second field effect transistor having one of its electrodes connected to a ONE bit line, said apparatus including: first means to apply a substantially constant voltage selectively to each of the ZERO and ONE bit lines; 9 second means to change the voltage condition on the other of the ZERO and ONE bit lines from that to which said first means is applying the substantially constant voltage; and third means to determine whether one of the first and second field effect transistors has a desired electrical characteristic when said first means is applying the substantially constant voltage to one of the ZERO and ONE bit lines and said second means is changing the voltage condition on the other of the ZERO and ONE bit lines and whether the other of the first and second field effect transistors has a desired electrical characteristic when said first means is applying the substantially constant voltage to the other of the ZERO and ONE bit lines and said second means is changing the voltage condition on the one of the ZERO and ONE bit lines.
Claim 8
Dependent Claim
107 words
The apparatus according to claim 5 in which: the first field effect transistor has its drain electrode connected to the ZERO bit line and its gate electrode connected to the ONE bit line and the second field effect transistor has its drain electrode connected to the ONE bit line and its gate electrode connected to the ZERO bit line; said first means applies the substantially constant voltage to the drain electrode of the field effect transistors havings its electrical characteristic determined; and said third means measures the current flow through the same field effect transistor at different voltages applied to its gate electrode by said second means.
Claim 9
Dependent Claim
221 words
The apparatus according to claim 5 in which: the first field effect transistor has its source electrode connected to the ZERO bit line and its drain and gate electrodes connected to a common voltage source with its source electrode also connected to the drain electrode of a third field effect transistor having its gate electrode connected to the ONE bit line and the second field effect transistor has its source electrode connected to the ONE bit line and its drain and gate electrodes connected to a common voltage source with its source electrode also connected to the drain electrode of a fourth field effect transistor having its gate electrode connected to the ZERO bit line; said first means applies the substantially constant voltage to the gate electrode of the field effect transistor of the third and fourth field effect transistors having its drain electrode connected to the source electrode of the field effect transistor having its electrical characteristic determined; said second means includes means to discharge for a first predetermined period of time the bit line connected to the source electrode of the field effect transistor having its electrical characteristic determined; and said third means includes means to determine the charge on the bit line a second predetermined period of time after said second means Ceases to discharge the bit line.
Claim 10
Dependent Claim
33 words
The apparatus according to claim 7 in which said discharge means includes: a transistor connecting the bit line to ground; and means to activate said transistor for the first predetermined period of time.
Claim 11
Dependent Claim
38 words
The apparatus according to claim 5 for determining the electrical characteristics of each of a plurality of memory cells arranged in a matrix including means to cause each of the cells to be activated at a different time.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-03-04 | 1977-09-03 | 1978-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-03-04 | 1981-09-03 | 1982-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-03-04 | 1985-09-03 | 1986-03-05 | $7700.00 | Window Closed / Lapsed |