US3727196A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic random access memory
Assignee: STMicroelectronics lnc USA
•
Filing: 1971-11-29
•
Granted: 1973-04-10
•
Expires: 1991-11-29
Abstract
Abstract A dynamic random access memory utilizing MOSFET transistors formed on a single semi-conductor chip is described. The random access memory utilizes 1,024 binary storage cells arrayed in rows and columns. Each row of cells has a read line and a write line. Each column of cells has one data line used for both read and write functions. Each cell is comprised of a write transistor and a pair of read transistors. The write transistor couples a capacitive storage node to the data line and is controlled by the write line. The read transistors are connected in series between the data line and VSS, and one is controlled by the read line and the other is controlled by the voltage on the storage node. A sense amplifier is provided for each data line and is used to apply data through the write transistor to the storage node, and to sense the state of the second read transistor controlled by the data stored on the storage node. The chip includes row and column address means for selecting a particular cell for either read or write mode. The chip also includes a number of features to prevent bipolar injection caused by forward biasing a PN junction as a result of capacitive coupling between various nodes in the circuit, and other features which prevent the loss of data from the storage node.
Inventors
- 👤 Kenny V Mc
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 02:50
CPC Classifications
H; H10; H10B; H10B12/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; G11C11/406; G11C11/4063; G11C11/407; G11C11/4076; G11C11/409; G11C11/4096
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
109 words
The memory system comprising: a plurality of dynamic storage cells arranged in a plurality of rows and columns, a data line for each column of storage cells, amplifier means for each column for transforming a voltage level above a reference level to one digital logic level and a voltage level below the reference level to another digital logic level, capacitive storage means at the input of the amplifier means, and switching means for connecting each of the data lines to the input of the respective amplifier means during a read cycle and for connecting the output of each amplifier means to the respective data line during a write cycle.
Claim 2
Dependent Claim
109 words
The memory system comprising: a plurality of dynamic storage cells arranged in a plurality of rows and columns, a data line for each column of storage cells, amplifier means for each column for transforming a voltage level above a reference level to one digital logic level and a voltage level below the reference level to another digital logic level, capacitive storage means at the input of the amplifier means, and switching means for connecting each of the data lines to the input of the respective amplifier means during a read cycle and for connecting the output of each amplifier means to the respective data line during a write cycle.
Claim 3
Dependent Claim
143 words
The memory system of claim 1 wherein the amplifier means comprises: an input stage comprised of a depletion mode first transistor, an enhancement mode second transistor, and an enhancement mode third transistor connected in series between source and drain voltages, the gate and source of the first transistor being common, the gate and drain of the third transistor being common, and the gate of the second transistor being the input for the two voltage levels, and a first output stage comprised of fourth and fifth enhancement mode transistors connected in series between source and drain voltages, the gate of the fourth transistor being connected to the drain of the second transistor, the gate of the fifth transistor being connected to the gate of the second transistor, and the source of the fourth transistor and the drain of the fifth transistor being the output.
Claim 4
Dependent Claim
65 words
The memory system of claim 2 further characterized by: a second output stage comprised of sixth and seventh enhancement mode transistors connected in series between the output of the first stage and a source voltage, the gate of the sixth transistor being connected to the drain of the second transistor, the gate of the seventh transistor being connected to the gate of the second transistor.
Claim 5
Dependent Claim
43 words
The memory system of claim 1 wherein the amplifier means comprises: a source follower input stage, an inverter stage providing regenerative feedback to the input stage, and a push-pull output stage driven by the outputs from the input stage and the inverter stage.
Claim 6
Dependent Claim
132 words
The memory system of claim 1 wherein the amplifier means comprises: an input stage comprised of an enhancement mode first transistor and a depletion mode second transistor connected in series between a drain and source voltage to provide a source follower, an intermediate stage comprised of a depletion mode third transistor and an enhancement mode fourth transistor connected between the drain and source voltages as an inverter stage, and an output stage comprised of fifth and sixth enhancement mode transistors connected between the drain and source voltages as a push-pull stage, the output of the source follower stage being connected to the gates of the fourth and sixth transistors, and the output of the intermediate stage being connected to the gate of the second transistor and the gate of the fifth transistor.
Claim 7
Dependent Claim
52 words
The memory system of claim 1 wherein the amplifier means compriseS: an inverter input stage having a relatively low gain to provide an input level shifter, at least two intermediate inverter stages having relatively high gain, and a push-pull output stage driven by the intermediate inverter stage to provide the logic levels.
Claim 8
Dependent Claim
63 words
The memory system of claim 6 wherein: each of the inverter stages comprises a depletion mode transistor and an enhancement mode transistor connected in series between drain and source voltages, the depletion mode devices having common gate and source terminals and being the output of the respective inverter stage, the gate of the enhancement mode device being the input of each inverter stage.
Claim 9
Dependent Claim
224 words
The memory system formed of FET transistors on a common semiconductor substrate comprising: a plurality of dynamic storage cells arranged in a plurality of rows and columns, a data line for each column of storage cells, at least one address line for each row of storage cells extending transversely of the data lines, the address lines and the data lines being capacitively coupled by stray capacitance, logic means for selectively driving each address line to a logic ''''0'''' level near the substrate voltage through a resistive path to the substrate voltage, a sense amplifier for each data line comprising a first output stage comprised of fourth and fifth enhancement mode transistors connected in series between source and drain voltages, the gate of the fourth transistor being connected to the drain of the second transistor, the gate of the fifth transistor being connected to the gate of the second transistor, and the source of the fourth transistor and the drain of the fifth transistor being the output, means coupling the output of the amplifier means to the data line during a write cycle, and the source of the fifth transistor of each sense amplifier being connected through said resistive path to the substrate voltage to prevent transient voltages from being impressed on the capacitively coupled lines when the lines are near the substrate voltage level.
Claim 10
Dependent Claim
224 words
The memory system formed of FET transistors on a common semiconductor substrate comprising: a plurality of dynamic storage cells arranged in a plurality of rows and columns, a data line for each column of storage cells, at least one address line for each row of storage cells extending transversely of the data lines, the address lines and the data lines being capacitively coupled by stray capacitance, logic means for selectively driving each address line to a logic ''''0'''' level near the substrate voltage through a resistive path to the substrate voltage, a sense amplifier for each data line comprising a first output stage comprised of fourth and fifth enhancement mode transistors connected in series between source and drain voltages, the gate of the fourth transistor being connected to the drain of the second transistor, the gate of the fifth transistor being connected to the gate of the second transistor, and the source of the fourth transistor and the drain of the fifth transistor being the output, means coupling the output of the amplifier means to the data line during a write cycle, and the source of the fifth transistor of each sense amplifier being connected through said resistive path to the substrate voltage to prevent transient voltages from being impressed on the capacitively coupled lines when the lines are near the substrate voltage level.
References Cited (Backward Citations)
US3576571A
Cited
US3514765A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-09 | 1976-10-09 | 1977-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-09 | 1980-10-09 | 1981-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-09 | 1984-10-09 | 1985-04-10 | $7700.00 | Window Closed / Lapsed |