US3576571A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory circuit using storage capacitance and field effect devices
Assignee: Boeing North American Inc
•
Filing: 1969-01-07
•
Granted: 1971-04-27
•
Expires: 1989-01-07
Abstract
Abstract The memory circuit includes a first capacitor that is charged through an address matrix to a potential representing a logical state during the write period of a memory cycle, and a second capacitor which is conditionally charged as a function of that logical state. The second capacitor conditionally provides charge to the first capacitor periodically to maintain the logical state of the first capacitor until it is altered during a subsequent write period. A MOS device is responsive to the charge on the first capacitor for driving an output terminal connected to one of its electrodes to a potential representing the logical state. The second capacitor has an electrode connected through a MOS switching device to the ungrounded side of the first capacitor for increasing the potential on the first capacitor and thereby increasing the potential to which the output terminal is driven.
Inventors
- 👤 Robert K Booher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:02
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/402
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
83 words
In combination: a storage capacitance, first means including field effect transistor means for charging said capacitance during a first interval to discrete voltage levels representing logic states as a function of logic states of information to be stored by said storage capacitance, second means including field effect transistor means responsive to a discrete voltage level representing one logic state for changing the voltage level of said capacitance during s subsequent interval, said second means connected to be responsive to said changed voltage level.
Claim 2
Dependent Claim
83 words
In combination: a storage capacitance, first means including field effect transistor means for charging said capacitance during a first interval to discrete voltage levels representing logic states as a function of logic states of information to be stored by said storage capacitance, second means including field effect transistor means responsive to a discrete voltage level representing one logic state for changing the voltage level of said capacitance during s subsequent interval, said second means connected to be responsive to said changed voltage level.
Claim 3
Dependent Claim
27 words
The combination recited in claim 1 wherein said second means for changing the voltage level comprises a digital circuit for connecting discrete voltage levels to said capacitance.
Claim 4
Dependent Claim
97 words
In combination: first field effect transistor means for charging a storage capacitance during a first interval to a voltage level as a function of logic information to be stored by said storage capacitance, second means including field effect transistor means responsive to one voltage level stored by said capacitance for changing the voltage level of said capacitance during s subsequent interval to a second discrete voltage level, an output connected to said second means responsive, and said second means connected to be responsive to said changed voltage level for providing an increased voltage level on said output.
Claim 5
Dependent Claim
97 words
In combination: first field effect transistor means for charging a storage capacitance during a first interval to a voltage level as a function of logic information to be stored by said storage capacitance, second means including field effect transistor means responsive to one voltage level stored by said capacitance for changing the voltage level of said capacitance during s subsequent interval to a second discrete voltage level, an output connected to said second means responsive, and said second means connected to be responsive to said changed voltage level for providing an increased voltage level on said output.
Claim 6
Dependent Claim
158 words
A memory circuit having a read/write memory cycle comprising means for charging a first capacitor to a potential representing a logical state, a second capacitor having one electrode connected to said first capacitor for increasing the charge on said first capacitor, switch means connected between said first capacitor and said one electrode of said second capacitor, said switch means becoming conductive as a function of the difference in the potentials on said first and second capacitors for connecting said second capacitor to said first capacitor, said second capacitor increasing the potential on said first capacitor when said switch means is conductive as a function of a change in the voltage potential on the other electrode of said second capacitor, field effect transistor mEans responsive to a potential on the first capacitor representing one logical state for changing the potential on the other electrode of the second capacitor and for indicating said logical state during said read/write memory cycle.
Claim 7
Dependent Claim
158 words
A memory circuit having a read/write memory cycle comprising means for charging a first capacitor to a potential representing a logical state, a second capacitor having one electrode connected to said first capacitor for increasing the charge on said first capacitor, switch means connected between said first capacitor and said one electrode of said second capacitor, said switch means becoming conductive as a function of the difference in the potentials on said first and second capacitors for connecting said second capacitor to said first capacitor, said second capacitor increasing the potential on said first capacitor when said switch means is conductive as a function of a change in the voltage potential on the other electrode of said second capacitor, field effect transistor mEans responsive to a potential on the first capacitor representing one logical state for changing the potential on the other electrode of the second capacitor and for indicating said logical state during said read/write memory cycle.
Claim 8
Dependent Claim
33 words
The combination recited in claim 4 wherein said first capacitor has one electrode connected to ground and an ungrounded electrode connected to said one electrode on said second capacitor through said switch means.
Claim 9
Dependent Claim
121 words
The combination recited in claim 5 including read signal source means connected to said field effect transistor means responsive, and wherein said field effect transistor means responsive comprises a first field effect transistor having one electrode connected to said read signal source means and a second electrode connected to said other electrode of said second capacitor, said first field effect transistor having a control electrode connected to the ungrounded electrode of said first capacitor for driving the second electrode of the first field effect transistor to a voltage level from said read signal source means as a function of the voltage potential on said first capacitor, said voltage level representing the logical state of the voltage potential on said first capacitor.
Claim 10
Dependent Claim
70 words
The combination recited in claim 6 where herein said field effect transistor means responsive further includes a second field effect transistor connected between a voltage source and the other electrode of said second capacitor including a control electrode connected to the ungrounded side of said first capacitor for turning said second field effect transistor on as a function of the potential on the first capacitor for charging the second capacitor.
Claim 11
Dependent Claim
100 words
The combination recited in claim 7 wherein said switch means comprises a third field effect transistor having a control and one electrode connected to said second field effect transistor and said second capacitor the other electrode of said third field effect transistor being connected to the ungrounded side of said first capacitor for turning on when the potential on said second capacitor is in excess of the potential of the first capacitor by an amount required to turn on the third field effect transistor for increasing the charge on the first capacitor during each read/write cycle of the memory circuit.
Claim 12
Dependent Claim
97 words
The combination recited in claim 8 including a plurality of said memory circuits connected to input and output terminals of a memory system through an address matrix comprising conductors and MOS devices having inherent capacitances, and wherein each memory circuit includes a MOS device connected between an output terminal of the memory circuit and said other electrode of said second capacitor for discharging at least a portion of said inherent capacitance to the voltage potential on the other electrode of said second capacitor during a reset period between the read and write periods of a memory cycle.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-26 | 1974-10-26 | 1975-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-26 | 1978-10-26 | 1979-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-26 | 1982-10-26 | 1983-04-27 | $7700.00 | Window Closed / Lapsed |