US3610967A
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Integrated memory cell circuit
Assignee: International Business Machines Corp
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Filing: 1970-02-27
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Granted: 1971-10-05
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Expires: 1990-02-27
Abstract
Abstract Method and means for constructing memory cell circuits, comprising the addition of a single diffusion to an IGFET wafer to form diodes in the drain or source regions of at least one of the FETS in the wafer, thus reducing the number of FETS in the cell and substantially reducing the area occupied by each cell. Three embodiments are disclosed, all using diodes as the input/output components of the cells and, in addition, one uses two diodes as the load, giving an exponential load characteristic, while another combines a diode and FET in the load to give a semiexponential load characteristic.
Inventors
- 👤 Thomas L Palfi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:08
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; H; H10; H10D; H10D84/00; H10D84/80; H10D84/811
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
296 words
A memory cell comprising: a. an integrated circuit comprising i. a body (20) of one conductivity type having a planar surface (22); ii. first, second and third separated regions (24,44,34) of the opposite conductivity type extending into said body from separate areas of said surface; iii. fourth and fifth regions (25,35) of said one conductivity type extending into said first (24) and third (34) regions, respectively, from areas of said planar surface entirely within the surface areas of said first and said third regions; iv. a first conductive gate electrode (49) insulated from but over the surface of the portion (20c) of said body between said first (24) and second (44) regions; v. a second conductive gate electrode (59) insulated from but over the surface of the portion (20d) of said body between said second (44) and said third (34) regions; vi. first, second and third contacts (28,44a,38) to said fourth (25), second (44) and fifth (35) regions respectively, and fourth and fifth contacts (37,27) between said first gate electrode (49) and said third region (34) and said second gate electrode (59) and said first region (24), respectively, such that said fourth region (25) and said first region (24) define a PN junction, said first region (24), said first gate electrode (49) and said second region (44) define the source, gate and drain of a fist insulated gate field effect transistor (13), said second region (44), said second gate electrode (59) and said third region (34) define the source, gate, and drain of a second insulated gate field effect transistor (12) and said fifth region (35) and said third region (34) define a PN junction; and b. means for connecting a bias source and a load impedance between said first (24) and said third (34) regions.
Claim 2
Dependent Claim
296 words
A memory cell comprising: a. an integrated circuit comprising i. a body (20) of one conductivity type having a planar surface (22); ii. first, second and third separated regions (24,44,34) of the opposite conductivity type extending into said body from separate areas of said surface; iii. fourth and fifth regions (25,35) of said one conductivity type extending into said first (24) and third (34) regions, respectively, from areas of said planar surface entirely within the surface areas of said first and said third regions; iv. a first conductive gate electrode (49) insulated from but over the surface of the portion (20c) of said body between said first (24) and second (44) regions; v. a second conductive gate electrode (59) insulated from but over the surface of the portion (20d) of said body between said second (44) and said third (34) regions; vi. first, second and third contacts (28,44a,38) to said fourth (25), second (44) and fifth (35) regions respectively, and fourth and fifth contacts (37,27) between said first gate electrode (49) and said third region (34) and said second gate electrode (59) and said first region (24), respectively, such that said fourth region (25) and said first region (24) define a PN junction, said first region (24), said first gate electrode (49) and said second region (44) define the source, gate and drain of a fist insulated gate field effect transistor (13), said second region (44), said second gate electrode (59) and said third region (34) define the source, gate, and drain of a second insulated gate field effect transistor (12) and said fifth region (35) and said third region (34) define a PN junction; and b. means for connecting a bias source and a load impedance between said first (24) and said third (34) regions.
Claim 3
Dependent Claim
184 words
A memory cell as in claim 1, wherein the load impedance comprises: c. sixth and seventh separated regions (23,33) of the opposite conductivity type, extending into said body (20) from separate areas of said surface (22); third and fourth conductive gate electrodes (29,39) insulated from but over the surface of said body between said sixth (23) and said first (24) regions and said seventh (33) and said third (34) regions, respectively, such that said sixth region (23), said third gate electrode (29) and said first region (24) define the source, gate and drain of a third insulated gate field effect transistor (11) and said seventh region (33), said fourth gate electrode (39) and said third region (34) define the source, gate and drain of a fourth field effect transistor (10); e. means connecting said third (29) and said fourth (39) conductive gate electrodes to said sixth (23) and said seventh (33) regions, respectively; f. sixth and seventh contacts (26,36) to said sixth (23) and said seventh (33) regions, respectively; and g. means connecting said sixth (26) and seventh (33) contacts to said bias source.
Claim 4
Dependent Claim
249 words
A memory cell as in claim 1, wherein the load impedance comprises: c. sixth and seventh separated regions (123,133) of the opposite conductivity type, extending into said body (120) from separate areas of said surface; d. third and fourth conductive gate electrodes (129,139) insulated from but dispersed over the surface of said body between said sixth (123) and said first (124) regions and said seventh (133) and said third (134) regions, respectively, such that said sixth region (123), said third gate electrode (129) and said first region (124) define the source, gate and drain of a third insulated gate field effect transistor (111), and said seventh region (133), said fourth gate electrode (139) and said third region (134) define the source, gate and drain of a fourth field effect transistor (110); e. means connecting said third and fourth conductive gate electrodes (129,139) to said sixth (123) and seventh (133) regions respectively; f. eighth and ninth regions (162,163) of said one conductivity type extending into said sixth (123) and said seventh (133) regions, respectively, from areas of said body surface entirely within the surface areas of said sixth (123) and said seventh (133) regions; g. sixth and seventh contacts (126, 136) to said eighth (162) and said ninth (163) regions, such said eighth (162) and said sixth (123) regions define a PN junction and said ninth (163) and said seventh (133) regions define a PN junction; and h. means connecting said sixth and seventh contacts (126,136) to said bias source.
Claim 5
Dependent Claim
215 words
A memory cell as in claim 1, wherein the load impedance comprises: c. sixth and seventh separated regions (223, 233) of the opposite conductivity type extending into said body (220) from separate areas of said surface; d. eighth and ninth regions (262, 263) of said one conductivity type extending into said sixth (223) and said seventh (233) regions, respectively, from areas of said body surface entirely within the surface areas of said sixth and said seventh regions (223,233); e. 10th and 11th regions (268,269) of said one conducTivity type extending into said first and said third regions (224, 234), respectively, from areas of said body surface entirely within the surface areas of said first and said third regions (224, 234); f. sixth and seventh contacts (226,236) to said eighth and said ninth regions (262,263) and means (272,273) connecting said sixth and said seventh regions (223,233) with said 10th and said 11th regions (268,269) such that said eighth and said sixth regions (262,223) and said 10th and said first regions (266,224) define two PN junctions (266,267) in series, and said ninth and said seventh regions (263,233) and said 11th and third regions (269,234) define two Pn junctions (264,265) in series; and g. means (240) connecting said sixth and seventh contacts (226, 236) to said bias source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-04 | 1975-04-05 | 1975-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-04 | 1979-04-05 | 1979-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-04 | 1983-04-05 | 1983-10-05 | $7700.00 | Window Closed / Lapsed |