JPS58144A
Expired / Lapsed
JP
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Fujitsu Ltd
•
Filing: 1981-06-25
•
Granted: —
•
Expires: 2001-06-25
Abstract
Abstract PURPOSE:To disable the measurement of monitoring elements in chips after cutting and prevent leakage of secrets in manufacturing technique, by a method wherein at least one of pads of monitoring elements is formed on adjacent chip. CONSTITUTION:Transistor Q in a chip 22 has gate electrode pad in an adjacent chip 23, and pads P5, P7 of resistors R1, R2 are in the adjacent chip 23. The transistor Q and resistors R1, R2 can be measured at wafer state, but not after cutting into chips as monitoring elements. Threby manufacturing process technique cannot be known by third parties.
Inventors
- 👤 Tomio Nakano
- 👤 中野 富男
- 👤 Yoshihiro Takemae
- 👤 義博 竹前
- 👤 Masao Nakano
- 👤 正夫 中野
- 👤 Norihisa Tsuge
- 👤 柘植 典久
- 👤 Takeshi Ohira
- 👤 大平 壮
Bibliographic Details
Application Number
—
Jurisdiction
JP
Data Source
google_patents
Last Synchronized
2026-10-25 22:51
CPC Classifications
H; H10; H10P; H10P74/00
Claims Analysis
Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.