US4595875A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Short detector for PROMS
Assignee: Advanced Micro Devices Inc
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Filing: 1983-12-22
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Granted: 1986-06-17
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Expires: 2003-12-22
Abstract
Abstract Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existance of leaky memory cells or shorts in the memory can be detected during testing. The test circuitry has no appreciable effect on the memory during normal operation of the memory.
Inventors
- 👤 Albert Chan
- 👤 Mark Fitzpatrick
- 👤 Don Goddard
- 👤 Robert J. Bosnyak
- 👤 Cyrus Tsui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:59
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/025; G11C29/04; G11C29/50; G11C17/00; G11C17/14; G11C2029/5006
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
106 words
In a semiconductor device comprising at least one programmable cell and at least one bit line, a circuit for detecting shorts or leakage currents comprising: means for receiving a selected test voltage; means for receiving a reference voltage; means, connected between said means for receiving a selected test voltage and each of said bit lines, for applying a predetermined portion of said selected test voltage to each of said bit lines; and means, connected between each of said bit lines and said means for receiving a reference voltage, for isolating said semiconductor device from said reference voltage when said selected test voltage is not being received.
Claim 2
Dependent Claim
106 words
In a semiconductor device comprising at least one programmable cell and at least one bit line, a circuit for detecting shorts or leakage currents comprising: means for receiving a selected test voltage; means for receiving a reference voltage; means, connected between said means for receiving a selected test voltage and each of said bit lines, for applying a predetermined portion of said selected test voltage to each of said bit lines; and means, connected between each of said bit lines and said means for receiving a reference voltage, for isolating said semiconductor device from said reference voltage when said selected test voltage is not being received.
Claim 3
Dependent Claim
69 words
The circuit in claim 1 wherein said means for applying a predetermined portion of said selected test voltage comprises a bipolar transistor for each bit line in said semiconductor device each said transistor having an emitter, a collector, and a base lead, said base lead being connected to said means for receiving a selected test voltage and to said collector, and said emitter being connected to said bit line.
Claim 4
Dependent Claim
31 words
The circuit in claim 1 wherein said means for isolating comprises a resistor connected between said means for receiving a selected test voltage and said means for receiving a reference voltage.
Claim 5
Dependent Claim
111 words
The circuit in claim 1 wherein said means for isolating comprises said means for applying and a resistor having two ends together with a plurality of diodes PD 1 , PD 2 . . . PD K where K is a positive integer, one end of said resistor being connected to said means for receiving a selected test voltage, the other end of said resistor being connected to the anode of PD 1 , the cathode of PD i being connected to the anode of PD i+1 for all i=1, . . . , K-1, and the cathode of PD K being connected to said means for receiving said reference voltage.
Claim 6
Dependent Claim
7 words
The circuit in claim 4 wherein K=2.
Claim 7
Dependent Claim
11 words
The circuit in claim 1 further comprising a reference voltage source.
Claim 8
Dependent Claim
12 words
the circuit in claim 6 wherein said reference voltage source is ground.
Claim 9
Dependent Claim
12 words
The circuit in claim 6 further comprising a selected test voltage source.
Claim 10
Dependent Claim
22 words
The circuit in claim 8 further comprising means for measuring the current flowing into said means for receiving said selected test voltage.
Claim 11
Independent Claim
109 words
The method of testing for shorts or current leakage in a semiconductor device having at least one bit line and at least one word line and associated addressing circuitry which comprises the steps of: applying a first selected voltage to each said bit line in said semiconductor device sufficient to disable said bit line's associated addressing circuitry; applying a second selected voltage to each said word line in said semiconductor device sufficient to disable said word line's associated addressing circuitry; applying a selected portion of a selected test voltage to each said bit line in said semiconductor device and measuring the total current that flows into said bit lines.
Claim 12
Independent Claim
109 words
The method of testing for shorts or current leakage in a semiconductor device having at least one bit line and at least one word line and associated addressing circuitry which comprises the steps of: applying a first selected voltage to each said bit line in said semiconductor device sufficient to disable said bit line's associated addressing circuitry; applying a second selected voltage to each said word line in said semiconductor device sufficient to disable said word line's associated addressing circuitry; applying a selected portion of a selected test voltage to each said bit line in said semiconductor device and measuring the total current that flows into said bit lines.
Claim 13
Independent Claim
130 words
The method of testing for shorts or current leakage in a semiconductor device having at least one bit line, at least one word line, and a decode transistor for each bit line, a decode transistor and a decode diode for each word line, and an input buffer having an output transistor, comprising the steps of turning off the decode transistor for each said bit line; turning off the decode transistor for each said word line by pulling each word line down through the decode diode for each word line by connecting the emitter of the output transistor of an input buffer to ground; applying a selected portion of a selected test voltage to each bit line in said device, and measuring the total current that flows into said bit lines.
Claim 14
Independent Claim
130 words
The method of testing for shorts or current leakage in a semiconductor device having at least one bit line, at least one word line, and a decode transistor for each bit line, a decode transistor and a decode diode for each word line, and an input buffer having an output transistor, comprising the steps of turning off the decode transistor for each said bit line; turning off the decode transistor for each said word line by pulling each word line down through the decode diode for each word line by connecting the emitter of the output transistor of an input buffer to ground; applying a selected portion of a selected test voltage to each bit line in said device, and measuring the total current that flows into said bit lines.
Claim 15
Independent Claim
141 words
The method of testing for shorts or current leakage in a semiconductor device having at least one bit line, at least one word line, a clamp transistor and a decode transistor for each bit line, a decode transistor and a decode diode for each word line, and an input buffer having an output transistor, which comprises the steps of: turning off the clamp transistor for each bit line; turning off the decode transistor for each bit line; turning off the decode transistor for each word line by pulling each word line down through the decode diode for each word line by connecting the emitter of the output transistor of an input buffer to ground; applying a selected portion of a selected test voltage to each bit line in said device; and measuring the total current that flows into said bit lines.
Claim 16
Independent Claim
141 words
The method of testing for shorts or current leakage in a semiconductor device having at least one bit line, at least one word line, a clamp transistor and a decode transistor for each bit line, a decode transistor and a decode diode for each word line, and an input buffer having an output transistor, which comprises the steps of: turning off the clamp transistor for each bit line; turning off the decode transistor for each bit line; turning off the decode transistor for each word line by pulling each word line down through the decode diode for each word line by connecting the emitter of the output transistor of an input buffer to ground; applying a selected portion of a selected test voltage to each bit line in said device; and measuring the total current that flows into said bit lines.
Claim 17
Dependent Claim
100 words
In a semiconductor device comprising at least one programmable cell and at least one bit line, a circuit for detecting shorts or leakage currents comprising: means for receiving a selected test voltage; means for receiving a reference voltage; means, connected between said means for receiving a selected test voltage and said bit line, for applying a predetermined portion of said selected test voltage to said bit line; and means, connected between said bit line and said means for receiving a reference voltage, for isolating said semiconductor device from said reference voltage when said selected test voltage is not being received.
Claim 18
Dependent Claim
100 words
In a semiconductor device comprising at least one programmable cell and at least one bit line, a circuit for detecting shorts or leakage currents comprising: means for receiving a selected test voltage; means for receiving a reference voltage; means, connected between said means for receiving a selected test voltage and said bit line, for applying a predetermined portion of said selected test voltage to said bit line; and means, connected between said bit line and said means for receiving a reference voltage, for isolating said semiconductor device from said reference voltage when said selected test voltage is not being received.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-16 | 1989-12-16 | 1990-06-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-16 | 1993-12-16 | 1994-06-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-16 | 1997-12-16 | 1998-06-17 | $7700.00 | Window Closed / Lapsed |