Method and arrangement for an operational check of a programmable logic array

Claim 3

The method of claim 1, and further comprising the steps of: first applying the second logic level to each input line; then sequentially disconnecting the product term lines from ground; and then evaluating the bit patterns appearing at the output lines.

Claim 6

The method of claim 3, and further comprising the steps of: first applying the second logic level to each input line; then sequentially disconnecting each group of product term lines from ground; and then evaluating the bit patterns appearing at the output lines.

Claim 7

Apparatus for performing a function check of a programmable logic array which has output lines, ground lines, input lines, product term lines intersecting the input lines and combined therewith to define an AND plane and intersecting and combined with the output lines to define an OR plane, the product term lines and the output lines having a reference potential applied thereto, and switching transistors at selected intersections of the product term lines and the input and output lines, the switching transistors in the AND plane having a control input connected to a respective input line and a controlled segment connected between the respective product term line and a ground line, the switching transistors in the OR plane having a control input connected to the respective product term line and a controlled segment connected to the respective output line and a ground line, said apparatus comprising: a test data generator including a plurality of outputs for connection to the input lines and operable to generate a sequence of bit patterns at said outputs; a plurality of switch elements each for connection to at least one respective product term line; a shift register including a plurality of stages each connected to and operable to control a respective switch element to effect connection and disconnection of the respective product term line with respect to ground; a clock operable to produce first clock pulses and second clock pulses at a higher frequency than that of said first clock pulses, said clock including a first clock pulse output connected to said test data generator and a second clock pulse output connected to said shift register; and a test data evaluator for connection to the output lines for evaluating the bit patterns which occur in response to the operation of said test data generator and said shift register.

Claim 8

Apparatus for performing a function check of a programmable logic array which has output lines, ground lines, input lines, product term lines intersecting the input lines and combined therewith to define an AND plane and intersecting and combined with the output lines to define an OR plane, the product term lines and the output lines having a reference potential applied thereto, and switching transistors at selected intersections of the product term lines and the input and output lines, the switching transistors in the AND plane having a control input connected to a respective input line and a controlled segment connected between the respective product term line and a ground line, the switching transistors in the OR plane having a control input connected to the respective product term line and a controlled segment connected to the respective output line and a ground line, said apparatus comprising: a test data generator including a plurality of outputs for connection to the input lines and operable to generate a sequence of bit patterns at said outputs; a plurality of switch elements each for connection to at least one respective product term line; a shift register including a plurality of stages each connected to and operable to control a respective switch element to effect connection and disconnection of the respective product term line with respect to ground; a clock operable to produce first clock pulses and second clock pulses at a higher frequency than that of said first clock pulses, said clock including a first clock pulse output connected to said test data generator and a second clock pulse output connected to said shift register; and a test data evaluator for connection to the output lines for evaluating the bit patterns which occur in response to the operation of said test data generator and said shift register.

Claim 9

The apparatus of claim 5, and further comprising: a flip-flop connected to and controlled by a stage of said shift register; an inverter connected to said flip-flop for inverting its output; a plurality of switching transistors as said switch elements each including a controlled section for connection across a respective pair of product term lines; and a plurality of first control transistors and a plurality of second control transistors, each of said first control transistors including a control input connected to said flip-flop via said inverter and each of said second control transistors including a control input connected directly to said flip-flop, each of said first control transistors including a controlled segment for connection across a first product term line of a respective pair and ground potential, and each of said second control transistors for connection across a second product term line of the respective pair and ground potential.

Claim 10

The apparatus of claim 5, wherein said test data generator comprises: a NOR gate including a plurality of inputs and an output; and a shift register connected to said inputs of said NOR gate and including a plurality of feedback connections via said output of said NOR gate, and a plurality of outputs forming said plurality of outputs of said test data generator.

Claim 11

The apparatus of claim 5, wherein each of said switch elements comprises: a pair of switching transistors each including a control input connected to the respective shift register stage, and a controlled section for connection between a respective product term line and ground potential.

Claim 12

The apparatus of claim 5, wherein: said test data evaluator comprises a signature register.

Claim 13

The apparatus of claim 5, wherein the output lines are divided into groups and wherein said test data evaluator comprises: a multiplexer including a plurality of groups of inputs, each comprising a plurality of inputs, for connection to respective groups of said output lines and a plurality of outputs, and operable to multiplex the groups of inputs to said outputs; and a signature register including a plurality of inputs connected to said plurality of outputs of said multiplexer.

Claim 14

The apparatus of claim 5, wherein the output lines are divided into groups and wherein said test data evaluator comprises: a multi-stage signature register; and a plurality of NAND gates each including an output connected to a respective stage of said signature register and a plurality of inputs for connection to a respective group of said output lines.