Programmable antifuse structure, process, logic cell and architecture for programmable integrated circuits

Claim 2

A process for fabricating antifuse-programmable gate array semiconductor devices having transistors and a plurality of antifuses having two terminals, comprising the steps of: depositing a first layer of titanium, or other refractory metal or metal silicide; depositing dielectrics; forming vias by means of etching; depositing at under 500° C. an antifuse layer approximately 30 nanometers to 400 nanometers said antifuse layer comprising an amorphous silicon-based dielectric layer; masking and etching said antifuse layer; depositing a second layer of a refractory metal or metal silicide.

Claim 3

The process of claim 1, wherein: said antifuse layer which is deposited comprises a stoichiometric or off-stoichiometric amorphous layer of silicon nitride (SiN x , where 0<×<1.4), or silicon oxide (SiO x , where 0<×≦2), or silicon oxynitride (SiO x N y , where 0<×<2 and 0<y<1.4).

Claim 4

The process of claim 2, wherein: the depositing and composition of said antifuse layer is such that a later heating of said antifuse layer in excess of 500° C. by an electrical current means or an energy beam means will cause a chemical reduction reaction between the refractory metal or metal silicide and silicon-based layers that yields more conductive material than is yielded non-conductive material, and such that there results a conductive compound between said refractory metal or metal silicide layers which constitutes a short circuit.

Claim 5

The process of claim 1, wherein: the step of depositing the first and/or second layers of refractory metal or metal silicide comprises depositing a material selected from the group consisting of titanium, titanium-tungsten, tantalum, or any combination of titanium, titanium-tungsten and tantalum.

Claim 6

The process of claim 1, further including: depositing a first metal layer before depositing said first layer of refractory metal or metal silicide.

Claim 7

The process of claim 1, further including: depositing a first metal layer before depositing said first layer of refractory metal or metal silicide; and masking and etching said first metal after depositing a first layer of titanium, or other refractory metal or metal silicide.

Claim 8

The process of claim 1, wherein: said first layer of refractory metal or metal silicide is deposited thicker than 50 nanometers.

Claim 9

The process of claim 1, further including: depositing any necessary planarization steps after depositing dielectrics.

Claim 10

The process of claim 1, wherein: the depositing of a silicon-based dielectric layer is such that it is in the range of approximately zero excess silicon to ninety-eight percent silicon in said dielectric layer.

Claim 11

The process of claim 1, wherein: said second layer of titanium, or other refractory metal or metal silicide is deposited thicker than 50 nanometers.

Claim 12

The process of claim 1, further including after depositing said second layer of refractory metal or metal silicide; depositing a first metal layer; and masking and etching said second metal layer with conventional processing thereafter.

Claim 13

The process of claim 11, further including: depositing an antifuse layer between said second metal layer and a third metal layer.

Claim 14

A process for fabricating antifuse-programmable gate array semiconductor devices having transistors and antifuses having two terminals, comprising the steps of: depositing a first layer of titanium more than 50 manometers thick; depositing dielectrics; forming vias by means of etching; depositing at under 500° C. an antifuse layer approximately 30 nanometers to 400 nanometers comprising an amorphous silicon-based dielectric layer; masking and etching said antifuse layer; and depositing a second layer of titanium more than 50 nanometers thick.

Claim 15

A process for fabricating antifuse-programmable gate array semiconductor devices having transistors and antifuses having two terminals, comprising the steps of: depositing a first layer of titanium more than 50 manometers thick; depositing dielectrics; forming vias by means of etching; depositing at under 500° C. an antifuse layer approximately 30 nanometers to 400 nanometers comprising an amorphous silicon-based dielectric layer; masking and etching said antifuse layer; and depositing a second layer of titanium more than 50 nanometers thick.

Claim 16

A gate array cell, comprising: two n-channel MOS transistors and two p-channel MOS transistors; a plurality of power supply lines; a plurality of input and output lines; and a plurality of antifuse elements, positioned and connected with said MOS transistors, said input, said output, and said power supply lines such that by programming selected antifuse elements the MOS transistors may be configured to produce logic functions between the input lines and output lines, said logic functions comprising NOR, NAND, NOT, and pass-gate, and combinations of NOR, NAND, NOT, and pass-gate.

Claim 17

A gate array cell, comprising: two n-channel MOS transistors and two p-channel MOS transistors; a plurality of power supply lines; a plurality of input and output lines; and a plurality of antifuse elements, positioned and connected with said MOS transistors, said input, said output, and said power supply lines such that by programming selected antifuse elements the MOS transistors may be configured to produce logic functions between the input lines and output lines, said logic functions comprising NOR, NAND, NOT, and pass-gate, and combinations of NOR, NAND, NOT, and pass-gate.

Claim 18

The gate array cell of claim 14, wherein: said antifuse elements comprise elements which have been fabricated by depositing, at under 500° C., an antifuse layer that is approximately 30 nanometers to 400 nanometers thick and lies between layers of refractory metal, said antifuse layer having a stoichiometric or off-stoichiometric amorphous silicon-based dielectric layer, such that a heating of said antifuse layer in excess of 500° C. by an electrical current means or an energy beam means will cause a chemical reduction reaction between the refractory metal and silicon-based dielectric layers such that there results a conductive compound between said refractory metal layers which substantially constitutes a short circuit.

Claim 19

The gate array cell of claim 14, further comprising: at least one transistor that enables the observation of at least one of the output lines such that testing of the gate array cell is enhanced.

Claim 20

The gate array cell of claim 14, further comprising: at least one data transfer transistor that enables implementation of memory cells by said MOS transistors when cross-coupled as a bistable latch, the data transfer transistors having a common gate controlled by a word line and antifuse elements able to connect the drains and sources of the data transfer transistors in a variety of ways to the input and output lines, bit lines, and word line.

Claim 21

A gate array cell, comprising: a first set of at least two n-channel MOS transistors and at least two p-channel MOS transistors; a plurality of power supply lines; a first plurality of input and output lines; a first plurality of antifuse elements, positioned and connected with the first MOS transistors and first input and output lines and power supply lines such that by programming selected first antifuse elements the first MOS transistors may be configured to produce logic functions between the input lines and output lines, said logic functions comprising NOR, NAND, NOT, and pass-gate, and combinations of NOR, NAND, NOT, and pass-gate; a second set of at least two n-channel MOS transistors and at least two p-channel MOS transistors; a second plurality of input and output lines; and a second plurality of antifuse elements, positioned and connected with the second MOS transistors and second input and output lines and power supply lines such that by programming selected second antifuse elements the second MOS transistors may be configured to produce logic functions between the input lines and output lines, said logic functions comprising NOR, NAND, NOT, and pass-gate, and combinations of NOR, NAND, NOT, and pass gate.

Claim 22

A gate array cell, comprising: a first set of at least two n-channel MOS transistors and at least two p-channel MOS transistors; a plurality of power supply lines; a first plurality of input and output lines; a first plurality of antifuse elements, positioned and connected with the first MOS transistors and first input and output lines and power supply lines such that by programming selected first antifuse elements the first MOS transistors may be configured to produce logic functions between the input lines and output lines, said logic functions comprising NOR, NAND, NOT, and pass-gate, and combinations of NOR, NAND, NOT, and pass-gate; a second set of at least two n-channel MOS transistors and at least two p-channel MOS transistors; a second plurality of input and output lines; and a second plurality of antifuse elements, positioned and connected with the second MOS transistors and second input and output lines and power supply lines such that by programming selected second antifuse elements the second MOS transistors may be configured to produce logic functions between the input lines and output lines, said logic functions comprising NOR, NAND, NOT, and pass-gate, and combinations of NOR, NAND, NOT, and pass gate.

Claim 23

A gate array cell, comprising: a first through fourth MOS transistor, the first and second MOS transistors being p-channel, the third and fourth MOS transistors being n-channel, the first and third MOS transistors having their gate electrodes in common with a first input line, the second and fourth MOS transistors having their gate electrodes in common with second input line, the first and second MOS transistors having the drain of the first MOS transistor connected to the source of the second MOS transistor and a first output line, the third and fourth MOS transistors having the drain of the third MOS transistor connected to the source of the fourth MOS transistor and a second output line, a third output line connected to the source of the first MOS transistor, a fourth output line connected to the drain of the second MOS transistor, a fifth output line connected to the source of the third MOS transistor, and a sixth output line connected to the drain of the fourth MOS transistor; a plurality of transfer and power lines; and a plurality of antifuse elements, positioned and connected such that by programming selected antifuse elements a variety of connection combinations can be independently established between the transfer lines, power lines, first and second input lines, and first through sixth output lines.

Claim 24

A gate array cell, comprising: a first through fourth MOS transistor, the first and second MOS transistors being p-channel, the third and fourth MOS transistors being n-channel, the first and third MOS transistors having their gate electrodes in common with a first input line, the second and fourth MOS transistors having their gate electrodes in common with second input line, the first and second MOS transistors having the drain of the first MOS transistor connected to the source of the second MOS transistor and a first output line, the third and fourth MOS transistors having the drain of the third MOS transistor connected to the source of the fourth MOS transistor and a second output line, a third output line connected to the source of the first MOS transistor, a fourth output line connected to the drain of the second MOS transistor, a fifth output line connected to the source of the third MOS transistor, and a sixth output line connected to the drain of the fourth MOS transistor; a plurality of transfer and power lines; and a plurality of antifuse elements, positioned and connected such that by programming selected antifuse elements a variety of connection combinations can be independently established between the transfer lines, power lines, first and second input lines, and first through sixth output lines.

Claim 25

The gate array cell of claim 19, wherein: the programming of selected antifuse elements is such that the MOS transistors can be configured to produce logic functions between the input lines and output lines, said logic functions comprising NOR, NAND, NOT, and pass-gate, and combinations of NOR, NAND, NOT, and pass-gate.

Claim 26

The gate array cell of claim 19, wherein: the antifuse elements have been fabricated by depositing, at under 500° C., an antifuse layer that is approximately 30 nanometers to 400 nanometers thick and lies between layers of refractory metal, said antifuse layer having a stoichiometric or off-stoichiometric amorphous silicon-oxide layer, such that a heating of said antifuse layer in excess of 500° C. by an electrical current means or an energy beam means will cause a chemical reduction reaction between the refractory metal and silicon-dioxide layers such that there results a conductive compound between said refractory metal layers which substantially constitutes a short circuit.

Claim 27

An improved programmable integrated circuit having an antifuse structure, the improvement comprising: a plurality of antifuse elements that have been fabricated by depositing, at under 500° C., an antifuse layer that is approximately 30 nanometers to 400 nanometers thick and lies between layers of titanium, said antifuse layer having an amorphous silicon-based dielectric layer, such that a heating of said antifuse layer in excess of 500° C. by an electrical current means or an energy beam means will cause a chemical reduction reaction between the titanium and silicon-based layers that yields more Ti 5 Si 3 , TiSi, and/or TiSi 2 than is yielded TiO, Ti 2 O 3 , Ti 3 O 5 , and/or TiO 2 , and such that there results a conductive compound between said titanium layers which substantially constitutes a short circuit.

Claim 28

An improved programmable integrated circuit having an antifuse structure, the improvement comprising: a plurality of antifuse elements that have been fabricated by depositing, at under 500° C., an antifuse layer that is approximately 30 nanometers to 400 nanometers thick and lies between layers of titanium, said antifuse layer having an amorphous silicon-based dielectric layer, such that a heating of said antifuse layer in excess of 500° C. by an electrical current means or an energy beam means will cause a chemical reduction reaction between the titanium and silicon-based layers that yields more Ti 5 Si 3 , TiSi, and/or TiSi 2 than is yielded TiO, Ti 2 O 3 , Ti 3 O 5 , and/or TiO 2 , and such that there results a conductive compound between said titanium layers which substantially constitutes a short circuit.