US5763898A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Above via metal-to-metal antifuses incorporating a tungsten via plug
Assignee: Microsemi SoC Corp
•
Filing: 1996-10-03
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Granted: 1998-06-09
•
Expires: 2016-10-03
Abstract
Abstract According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers. According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage. According to a third aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer disposed over a plug of an electrically conductive material disposed between two metallization layers.
Inventors
- 👤 Abdul R. Forouhi
- 👤 Frank W. Hawley
- 👤 John L. McCollum
- 👤 Yeouchung Yen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:36
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491; H10W20/01; H10W20/031; H10W20/064; H10W20/065; H10W20/41; H10W20/425
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
129 words
An electrically programmable antifuse disposed on an integrated circuit comprising: a first metalization layer disposed on an insulating portion of said integrated circuit; an interlayer dielectric layer disposed over said first metalization layer; a via having substantially parallel sidewalls completely penetrating said interlayer dielectric layer and exposing said first metalization layer; a layer of an electrically conductive material disposed in said via and in electrical contact with said first metalization layer, said electrically conductive material filling said via; a flat planar antifuse material layer disposed over said layer of electrically conductive material, said antifuse material layer including a layer of amorphous silicon sandwiched between a first and a second layer of an insulating material other than amorphous silicon; and a second metalization layer disposed over said antifuse material layer.
Claim 2
Dependent Claim
129 words
An electrically programmable antifuse disposed on an integrated circuit comprising: a first metalization layer disposed on an insulating portion of said integrated circuit; an interlayer dielectric layer disposed over said first metalization layer; a via having substantially parallel sidewalls completely penetrating said interlayer dielectric layer and exposing said first metalization layer; a layer of an electrically conductive material disposed in said via and in electrical contact with said first metalization layer, said electrically conductive material filling said via; a flat planar antifuse material layer disposed over said layer of electrically conductive material, said antifuse material layer including a layer of amorphous silicon sandwiched between a first and a second layer of an insulating material other than amorphous silicon; and a second metalization layer disposed over said antifuse material layer.
Claim 3
Dependent Claim
13 words
An antifuse according to claim 1 wherein said insulating material is silicon nitride.
Claim 4
Dependent Claim
17 words
An antifuse according to claim 2 further comprising an etch-stop/barrier layer disposed over said antifuse material layer.
Claim 5
Dependent Claim
39 words
An antifuse according to claim 3 wherein said etch-stop/barrier layer is fabricated of a material selected from the group consisting of: TiN, TiW, TiWN, W, TiC, WC and combinations of two or more of any of the foregoing materials.
Claim 6
Dependent Claim
155 words
An electrically programmable antifuse disposed on an integrated circuit comprising: a first metalization layer disposed on an insulating portion of said integrated circuit; an interlayer dielectric layer disposed over said first metalization layer; a via having substantially parallel sidewalls completely penetrating said interlayer dielectric layer and exposing said first metalization layer; a layer of an electrically conductive material disposed in said via and in electrical contact with said first metalization layer; an electrically conductive barrier layer disposed in said via over said layer of electrically conductive material, said electrically conductive barrier layer filling said via; a flat planar antifuse material layer disposed over said layer of electrically conductive material and in contact with said electrically conductive barrier layer, said antifuse material layer including a layer of amorphous silicon sandwiched between a first and a second layer of an insulating material other than amorphous silicon; and a second metalization layer disposed over said antifuse material layer.
Claim 7
Dependent Claim
155 words
An electrically programmable antifuse disposed on an integrated circuit comprising: a first metalization layer disposed on an insulating portion of said integrated circuit; an interlayer dielectric layer disposed over said first metalization layer; a via having substantially parallel sidewalls completely penetrating said interlayer dielectric layer and exposing said first metalization layer; a layer of an electrically conductive material disposed in said via and in electrical contact with said first metalization layer; an electrically conductive barrier layer disposed in said via over said layer of electrically conductive material, said electrically conductive barrier layer filling said via; a flat planar antifuse material layer disposed over said layer of electrically conductive material and in contact with said electrically conductive barrier layer, said antifuse material layer including a layer of amorphous silicon sandwiched between a first and a second layer of an insulating material other than amorphous silicon; and a second metalization layer disposed over said antifuse material layer.
Claim 8
Dependent Claim
13 words
An antifuse according to claim 5 wherein said insulating material is silicon nitride.
Claim 9
Dependent Claim
18 words
An antifuse according to claim 6 further comprising an etch- stop/barrier layer disposed over said antifuse material layer.
Claim 10
Dependent Claim
39 words
An antifuse according to claim 7 wherein said etch-stop/barrier layer is fabricated of a material selected from the group consisting of: TiN, TiW, TiWN, W, TiC, WC and combinations of two or more of any of the foregoing materials.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-08 | 2001-12-08 | 2002-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-08 | 2005-12-08 | 2006-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-08 | 2009-12-08 | 2010-06-09 | $7700.00 | Window Closed / Lapsed |