Patent US5610089A successfully refreshed from Google Patents.
US5610089A
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Method of fabrication of semiconductor integrated circuit device
Assignee: Hitachi Ltd
•
Filing: 1995-04-27
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Granted: 1997-03-11
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Expires: 2015-04-27
Abstract
Abstract Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.
Inventors
- 👤 Hidetoshi Iwai
- 👤 Kazumichi Mitsusada
- 👤 Masamichi Ishihara
- 👤 Tetsuro Matsumoto
- 👤 Kazuyuki Miyazawa
- 👤 Hisao Katto
- 👤 Kousuke Okuyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:46
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/605; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0184; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10D84/8312; H10D84/8316; H10D84/835
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
300 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: providing a semiconductor substrate having an output MISFET forming region and an internal circuit forming region, with a first gate insulating film on said output MISFET forming region, and a first gate electrode of a first output MISFET on said first gate insulating film, and with a second gate insulating film on said internal circuit forming region, and a second gate electrode of a first MISFET on said second gate insulating film; introducing into said output MISFET forming region an impurity in self-alignment with said first gate electrode to form a first semiconductor region of a first conductivity type such that a pn-junction is formed between said first semiconductor region and said semiconductor substrate; introducing into said internal circuit forming region an impurity in self-alignment with said second gate electrode to form a second semiconductor region of said first conductivity type such that a pn-junction is formed between said second semiconductor region and said semiconductor substrate and such that an impurity concentration of said first semiconductor region is higher than that of said second semiconductor region; forming a third semiconductor region of said first conductivity type in said internal circuit forming region by introducing an impurity in said internal circuit forming region; and forming an output pad, on said semiconductor substrate, that is electrically connected to said first semiconductor region, said second semiconductor region being formed between said third semiconductor region and a channel forming region of said first MISFET, an impurity concentration of said third semiconductor region being higher than that of said second semiconductor region, said second and third semiconductor regions serving as a drain region of said first MISFET, and said first semiconductor region serving as a drain region of said first output MISFET.
Claim 2
Independent Claim
300 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: providing a semiconductor substrate having an output MISFET forming region and an internal circuit forming region, with a first gate insulating film on said output MISFET forming region, and a first gate electrode of a first output MISFET on said first gate insulating film, and with a second gate insulating film on said internal circuit forming region, and a second gate electrode of a first MISFET on said second gate insulating film; introducing into said output MISFET forming region an impurity in self-alignment with said first gate electrode to form a first semiconductor region of a first conductivity type such that a pn-junction is formed between said first semiconductor region and said semiconductor substrate; introducing into said internal circuit forming region an impurity in self-alignment with said second gate electrode to form a second semiconductor region of said first conductivity type such that a pn-junction is formed between said second semiconductor region and said semiconductor substrate and such that an impurity concentration of said first semiconductor region is higher than that of said second semiconductor region; forming a third semiconductor region of said first conductivity type in said internal circuit forming region by introducing an impurity in said internal circuit forming region; and forming an output pad, on said semiconductor substrate, that is electrically connected to said first semiconductor region, said second semiconductor region being formed between said third semiconductor region and a channel forming region of said first MISFET, an impurity concentration of said third semiconductor region being higher than that of said second semiconductor region, said second and third semiconductor regions serving as a drain region of said first MISFET, and said first semiconductor region serving as a drain region of said first output MISFET.
Claim 3
Dependent Claim
50 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said pn-junction formed between the first semiconductor region and said semiconductor substrate extends under said first gate electrode, and said pn-junction between said second semiconductor region and said semiconductor substrate extends under the second gate electrode.
Claim 4
Dependent Claim
48 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein in said introducing step to form said second semiconductor region said impurity is introduced into said internal circuit forming region by using, as a mask, a mask layer covering said output MISFET forming region.
Claim 5
Dependent Claim
37 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said third semiconductor region is formed by introducing into said internal circuit forming region an impurity in self-alignment with said second gate electrode.
Claim 6
Independent Claim
421 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: providing a semiconductor substrate having an output MISFET forming region and an internal circuit forming region, with a first gate insulating film on said output MISFET forming region, and a first gate electrode of a first output MISFET on said first gate insulating film, and with a second gate insulating film on said internal circuit forming region, and a second gate electrode of a first MISFET on said second gate insulating film; forming a first semiconductor region of a first conductivity type in said output MISFET forming region and a second semiconductor region of said first conductivity type in said internal circuit forming region by introducing an impurity in self-alignment with said first gate electrode and in self-alignment with said second gate electrode; forming first side wall spacers on both side surfaces of said first gate electrode in self-alignment with said first gate electrode and second side wall spacers on both side surfaces of said second gate electrode in self-alignment with said second gate electrode; forming a third semiconductor region of said first conductivity type in said output MISFET forming region and a fourth semiconductor region of said first conductivity type in said internal circuit forming region by introducing an impurity in self-alignment with said first side wall spacer and in self-alignment with said second side wall spacer such that said first semiconductor region is formed between said third semiconductor region and a channel forming region of said first output MISFET and such that said second semiconductor region is formed between said fourth semiconductor region and a channel forming region of said first MISFET; forming a fifth semiconductor region of said first conductivity type in said output MISFET forming region so as to surround said first and third semiconductor regions in said semiconductor substrate by introducing an impurity in said output MISFET forming region; and forming an output pad, on said semiconductor substrate, that is electrically connected to said fifth semiconductor region, wherein an impurity concentration of said third semiconductor region is higher than that of said first semiconductor region, an impurity concentration of said fifth semiconductor region is higher than that of said first semiconductor region, and said first, third, and fifth semiconductor regions serve as a drain region of said output MISFET, and wherein an impurity concentration of said fourth semiconductor region is higher than that of said second semiconductor region, said second and fourth semiconductor regions serving as a drain region of said first MISFET.
Claim 7
Independent Claim
421 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: providing a semiconductor substrate having an output MISFET forming region and an internal circuit forming region, with a first gate insulating film on said output MISFET forming region, and a first gate electrode of a first output MISFET on said first gate insulating film, and with a second gate insulating film on said internal circuit forming region, and a second gate electrode of a first MISFET on said second gate insulating film; forming a first semiconductor region of a first conductivity type in said output MISFET forming region and a second semiconductor region of said first conductivity type in said internal circuit forming region by introducing an impurity in self-alignment with said first gate electrode and in self-alignment with said second gate electrode; forming first side wall spacers on both side surfaces of said first gate electrode in self-alignment with said first gate electrode and second side wall spacers on both side surfaces of said second gate electrode in self-alignment with said second gate electrode; forming a third semiconductor region of said first conductivity type in said output MISFET forming region and a fourth semiconductor region of said first conductivity type in said internal circuit forming region by introducing an impurity in self-alignment with said first side wall spacer and in self-alignment with said second side wall spacer such that said first semiconductor region is formed between said third semiconductor region and a channel forming region of said first output MISFET and such that said second semiconductor region is formed between said fourth semiconductor region and a channel forming region of said first MISFET; forming a fifth semiconductor region of said first conductivity type in said output MISFET forming region so as to surround said first and third semiconductor regions in said semiconductor substrate by introducing an impurity in said output MISFET forming region; and forming an output pad, on said semiconductor substrate, that is electrically connected to said fifth semiconductor region, wherein an impurity concentration of said third semiconductor region is higher than that of said first semiconductor region, an impurity concentration of said fifth semiconductor region is higher than that of said first semiconductor region, and said first, third, and fifth semiconductor regions serve as a drain region of said output MISFET, and wherein an impurity concentration of said fourth semiconductor region is higher than that of said second semiconductor region, said second and fourth semiconductor regions serving as a drain region of said first MISFET.
Claim 8
Independent Claim
420 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: providing a semiconductor substrate having an output MISFET forming region, an internal circuit forming region and an input protective MISFET forming region, with a first gate insulating film on said output MISFET forming region, and a first gate electrode of an output MISFET on said first gate insulating film, with a second gate insulating film on said internal circuit forming region, and a second gate electrode of a first MISFET on said second gate insulating film, and with a third gate insulating film on said input protective MISFET forming region, and a third gate electrode of an input protective MISFET on said third gate insulating film; introducing, into said output MISFET forming region and said input protective MISFET forming region, an impurity in self-alignment with said first gate electrode and said third gate electrode to form a first semiconductor region and a fourth semiconductor region such that a pn-junction is formed, under said first gate electrode, between said first semiconductor region and said semiconductor substrate and such that a pn-junction is formed, under said third gate electrode, between said fourth semiconductor region and said semiconductor substrate, said first and fourth semiconductor regions being of a first conductivity type; introducing into said internal circuit forming region an impurity in self-alignment with said second gate electrode to form a second semiconductor region of said first conductivity type such that a pn-junction is formed, under said second gate electrode, between said second semiconductor region and said semiconductor substrate and such that an impurity concentration of said first and fourth semiconductor regions is higher than that of said second semiconductor region; forming a third semiconductor region of said first conductivity type in said internal circuit forming region by introducing an impurity in said internal circuit forming region; and forming an output pad and an input pad on said semiconductor substrate, said output pad and said input pad being electrically connected to said first semiconductor region and said fourth semiconductor region, respectively, said second semiconductor region being formed between said third semiconductor region and a channel forming region of said first MISFET, an impurity concentration of said third semiconductor region being higher than that of said second semiconductor region, said second and third semiconductor regions serving as a drain region of said first MISFET, and said fourth semiconductor region serving as a drain region of said input protective MISFET, said first semiconductor region serving as a drain region of said output MISFET.
Claim 9
Independent Claim
420 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: providing a semiconductor substrate having an output MISFET forming region, an internal circuit forming region and an input protective MISFET forming region, with a first gate insulating film on said output MISFET forming region, and a first gate electrode of an output MISFET on said first gate insulating film, with a second gate insulating film on said internal circuit forming region, and a second gate electrode of a first MISFET on said second gate insulating film, and with a third gate insulating film on said input protective MISFET forming region, and a third gate electrode of an input protective MISFET on said third gate insulating film; introducing, into said output MISFET forming region and said input protective MISFET forming region, an impurity in self-alignment with said first gate electrode and said third gate electrode to form a first semiconductor region and a fourth semiconductor region such that a pn-junction is formed, under said first gate electrode, between said first semiconductor region and said semiconductor substrate and such that a pn-junction is formed, under said third gate electrode, between said fourth semiconductor region and said semiconductor substrate, said first and fourth semiconductor regions being of a first conductivity type; introducing into said internal circuit forming region an impurity in self-alignment with said second gate electrode to form a second semiconductor region of said first conductivity type such that a pn-junction is formed, under said second gate electrode, between said second semiconductor region and said semiconductor substrate and such that an impurity concentration of said first and fourth semiconductor regions is higher than that of said second semiconductor region; forming a third semiconductor region of said first conductivity type in said internal circuit forming region by introducing an impurity in said internal circuit forming region; and forming an output pad and an input pad on said semiconductor substrate, said output pad and said input pad being electrically connected to said first semiconductor region and said fourth semiconductor region, respectively, said second semiconductor region being formed between said third semiconductor region and a channel forming region of said first MISFET, an impurity concentration of said third semiconductor region being higher than that of said second semiconductor region, said second and third semiconductor regions serving as a drain region of said first MISFET, and said fourth semiconductor region serving as a drain region of said input protective MISFET, said first semiconductor region serving as a drain region of said output MISFET.
Claim 10
Dependent Claim
56 words
A method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein in said introducing step to form said second semiconductor region said impurity is introduced into said internal circuit forming region by using, as a mask, a mask layer covering both said output MISFET forming region and said input protective MISFET forming region.
Claim 11
Dependent Claim
37 words
A method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein said third semiconductor region is formed by introducing into said internal circuit forming region an impurity in self-alignment with said second gate electrode.
Claim 12
Dependent Claim
73 words
A method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein, in said introducing step to form said first and fourth semiconductor regions, said impurity is introduced into said input protective MISFET forming region, said output MISFET forming region, and a resistor element forming region of said semiconductor substrate to form a resistor element, and wherein said resistor element is formed between said fourth semiconductor region and said input pad.
Claim 13
Independent Claim
319 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: providing a semiconductor substrate having an input protective MISFET forming region and an internal circuit forming region, with a first gate insulating film on said input protective MISFET forming region, and a first gate electrode of an input protective MISFET on said first gate insulating film, and with a second gate insulating film on said internal circuit forming region, and a second gate electrode of a first MISFET on said second gate insulating film; introducing into said input protective MISFET forming region an impurity in self-alignment with said first gate electrode to form a first semiconductor region of a first conductivity type such that a pn-junction is formed, under said first gate electrode, between said first semiconductor region and said semiconductor substrate; introducing into said internal circuit forming region an impurity in self-alignment with said second gate electrode to form a second semiconductor region of said first conductivity type such that a pn-junction is formed, under said second gate electrode, between said second semiconductor region and said semiconductor substrate and such that an impurity concentration of said first semiconductor region is higher than that of said second semiconductor region; forming a third semiconductor region of said first conductivity type in said internal circuit forming region by introducing an impurity in said internal circuit forming region; and forming an input pad, on said semiconductor substrate, which is electrically connected to both said first semiconductor region and said first gate electrode, said second semiconductor region being formed between said third semiconductor region and a channel forming region of said first MISFET, an impurity concentration of said third semiconductor region being higher than that of said second semiconductor region, said second and third semiconductor regions serving as a drain region of said first MISFET, and said first semiconductor region serving as a drain region of said input protective MISFET.
Claim 14
Independent Claim
319 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: providing a semiconductor substrate having an input protective MISFET forming region and an internal circuit forming region, with a first gate insulating film on said input protective MISFET forming region, and a first gate electrode of an input protective MISFET on said first gate insulating film, and with a second gate insulating film on said internal circuit forming region, and a second gate electrode of a first MISFET on said second gate insulating film; introducing into said input protective MISFET forming region an impurity in self-alignment with said first gate electrode to form a first semiconductor region of a first conductivity type such that a pn-junction is formed, under said first gate electrode, between said first semiconductor region and said semiconductor substrate; introducing into said internal circuit forming region an impurity in self-alignment with said second gate electrode to form a second semiconductor region of said first conductivity type such that a pn-junction is formed, under said second gate electrode, between said second semiconductor region and said semiconductor substrate and such that an impurity concentration of said first semiconductor region is higher than that of said second semiconductor region; forming a third semiconductor region of said first conductivity type in said internal circuit forming region by introducing an impurity in said internal circuit forming region; and forming an input pad, on said semiconductor substrate, which is electrically connected to both said first semiconductor region and said first gate electrode, said second semiconductor region being formed between said third semiconductor region and a channel forming region of said first MISFET, an impurity concentration of said third semiconductor region being higher than that of said second semiconductor region, said second and third semiconductor regions serving as a drain region of said first MISFET, and said first semiconductor region serving as a drain region of said input protective MISFET.
Claim 15
Dependent Claim
49 words
A method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein, in said introducing step to form said second semiconductor region, said impurity is introduced into said internal circuit forming region by using, as a mask, a mask layer covering said input protective MISFET forming region.
Claim 16
Dependent Claim
37 words
A method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein said third semiconductor region is formed by introducing into said internal circuit forming region an impurity in self-alignment with said second gate electrode.
Claim 17
Dependent Claim
68 words
A method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein, in said introducing step to form said first semiconductor region, said impurity is introduced into both said input protective MISFET forming region and a resistor element forming a region of said semiconductor substrate to form a resistor element, and wherein said resistor element is formed between said first semiconductor region and said input pad.
Claim 18
Independent Claim
313 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: providing a semiconductor substrate having a second MISFET forming region and an internal circuit forming region, with a first gate insulating film on said second MISFET forming region, and a first gate electrode of a second MISFET on said first gate insulating film, and with a second gate insulating film on said internal circuit forming region, and a second gate electrode of a first MISFET on said second gate insulating film; introducing into said second MISFET forming region at least one impurity in self-alignment with said first gate electrode to form respectively at least a first semiconductor region of a first conductivity type such that a pn-junction is formed, under said first gate electrode, between said first semiconductor region and said semiconductor substrate; introducing into said internal circuit forming region an impurity in self-alignment with said second gate electrode to form a second semiconductor region of said first conductivity type such that a pn-junction is formed, under said second gate electrode, between said second semiconductor region and said semiconductor substrate and such that an impurity concentration of said first semiconductor region is higher than that of said second semiconductor region; forming a third semiconductor region of said first conductivity type in said internal circuit forming region by introducing an impurity in said internal circuit forming region; and forming a first bonding pad, on said semiconductor substrate, being electrically connected to said first semiconductor region, said second semiconductor region being formed between said third semiconductor region and a channel forming region of said first MISFET, an impurity concentration of said third semiconductor region being higher than that of said second semiconductor region, said second and third semiconductor regions serving as a drain region of said first MISFET, and said first semiconductor region serving as a drain region of said second MISFET.
Claim 19
Independent Claim
313 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: providing a semiconductor substrate having a second MISFET forming region and an internal circuit forming region, with a first gate insulating film on said second MISFET forming region, and a first gate electrode of a second MISFET on said first gate insulating film, and with a second gate insulating film on said internal circuit forming region, and a second gate electrode of a first MISFET on said second gate insulating film; introducing into said second MISFET forming region at least one impurity in self-alignment with said first gate electrode to form respectively at least a first semiconductor region of a first conductivity type such that a pn-junction is formed, under said first gate electrode, between said first semiconductor region and said semiconductor substrate; introducing into said internal circuit forming region an impurity in self-alignment with said second gate electrode to form a second semiconductor region of said first conductivity type such that a pn-junction is formed, under said second gate electrode, between said second semiconductor region and said semiconductor substrate and such that an impurity concentration of said first semiconductor region is higher than that of said second semiconductor region; forming a third semiconductor region of said first conductivity type in said internal circuit forming region by introducing an impurity in said internal circuit forming region; and forming a first bonding pad, on said semiconductor substrate, being electrically connected to said first semiconductor region, said second semiconductor region being formed between said third semiconductor region and a channel forming region of said first MISFET, an impurity concentration of said third semiconductor region being higher than that of said second semiconductor region, said second and third semiconductor regions serving as a drain region of said first MISFET, and said first semiconductor region serving as a drain region of said second MISFET.
Claim 20
Dependent Claim
21 words
A method of manufacturing a semiconductor integrated circuit device according to claim 14, wherein said second MISFET is an output MISFET.
Claim 21
Dependent Claim
22 words
A method of manufacturing a semiconductor integrated circuit device according to claim 14, wherein said second MISFET is an input protective MISFET.
Claim 22
Dependent Claim
205 words
A method of manufacturing a semiconductor integrated circuit device according to claim 14, wherein said semiconductor substrate further has a third MISFET forming region with a third gate insulating film on said third MISFET forming region, and a third gate electrode of a third MISFET on said third gate insulating film, wherein, in said impurity introducing step for forming said first semiconductor region, said impurity is introduced into both said second MISFET forming region and said third MISFET forming region in self-alignment with said first gate electrode and said third gate electrode to form said first semiconductor region and a fourth semiconductor region of said first conductivity type such that a pn-junction is formed, under said third gate electrode, between said fourth semiconductor region and said semiconductor substrate, wherein, in said first bonding pad forming step, said first bonding pad and a second bonding pad are formed on said semiconductor substrate, wherein said fourth semiconductor region has an impurity concentration higher than that of said second semiconductor region, is electrically connected to said second bonding pad, and serves as a drain region of said third MISFET, and wherein said second MISFET and said third MISFET are an output MISFET and an input protective MISFET, respectively.
Claim 23
Dependent Claim
37 words
A method of manufacturing a semiconductor integrated circuit device according to claim 14, wherein one impurity is introduced into the second MISFET forming region in self-alignment with said first gate electrode to form the first semiconductor region.
Claim 24
Dependent Claim
82 words
A method of manufacturing a semiconductor integrated circuit device according to claim 14, wherein three impurities are introduced into said second MISFET forming region so as to form said first semiconductor region and fourth and fifth semiconductor regions, respectively, the fourth semiconductor region being formed such that the first semiconductor region is between the fourth semiconductor region and a channel-forming region of the second MISFET, and the fifth semiconductor region being formed so as to surround the first and fourth semiconductor regions.
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