US4475280A
Expired / Lapsed
US
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Method of making an integrated circuit incorporating low voltage and high voltage semiconductor devices
Assignee: Intersil Corp
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Filing: 1982-12-17
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Granted: 1984-10-09
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Expires: 2002-12-17
Abstract
Abstract An integrated circuit incorporating high voltage semiconductor devices which are controlled by low voltage semiconductor devices is disclosed, including a method for making the same. The low voltage devices which are capable of realizing complex logic functions on the same chip are realized with only one simple extra step in the fabrication process as compared with the process used to fabricate discrete high voltage power transistors. The process addition to implant the low voltage device does not significantly degrade the original capability associated with discrete power transistors. Both laterally developed and vertically developed devices are described. The integrated circuit combines I 2 L logic with power Darlington transistors. A large area ion implantation permits one to fabricate both low and high voltage devices on one substrate. The resulting integrated circuit permits a plurality of loads to be controlled by a simple or complex control function.
Inventors
- 👤 Louis J. Ragonese
- 👤 Nicholas A. Schmitz
- 👤 Saverio F. Bevacqua
- 👤 King Owyang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:19
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10D84/658; H03; H03K; H03K17/00; H03K17/28; H03K17/51; H03K17/56; H03K17/60; H03K17/78; H03K17/795; H10D84/63; H10D84/641; H10D84/642
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
189 words
A method for making an integrated circuit of the type including low voltage and high voltage semiconductor devices on a single substrate comprising: A. providing a substrate having an underlying highly doped first region of a first conductivity type, with a second moderately doped region of said first conductivity type overlying said first region; B. increasing the doping level with device patterning from the upper surface of said substrate within said second region to form a third, patterned region; C. simultaneously diffusing an impurity of a second conductivity type with device patterning into said second and third patterned regions to produce a fourth, device patterned region, the portions of said fourth region overlying said third region having a depth differing from those portions of said fourth region overlying said second region; and D. simultaneously diffusing an impurity of said first conductivity type with device patterning to produce a fifth, device patterned region overlying said fourth region to form vertically developed semiconductor devices wherein said developed devices formed from said third, fourth and fifth regions have a vertical geometry differing from devices formed from said second, fourth and fifth regions.
Claim 2
Independent Claim
189 words
A method for making an integrated circuit of the type including low voltage and high voltage semiconductor devices on a single substrate comprising: A. providing a substrate having an underlying highly doped first region of a first conductivity type, with a second moderately doped region of said first conductivity type overlying said first region; B. increasing the doping level with device patterning from the upper surface of said substrate within said second region to form a third, patterned region; C. simultaneously diffusing an impurity of a second conductivity type with device patterning into said second and third patterned regions to produce a fourth, device patterned region, the portions of said fourth region overlying said third region having a depth differing from those portions of said fourth region overlying said second region; and D. simultaneously diffusing an impurity of said first conductivity type with device patterning to produce a fifth, device patterned region overlying said fourth region to form vertically developed semiconductor devices wherein said developed devices formed from said third, fourth and fifth regions have a vertical geometry differing from devices formed from said second, fourth and fifth regions.
Claim 3
Dependent Claim
32 words
The method of claim 1 wherein said doping level is increased in said third region in respect to said second region by ion implantation of an impurity of said first conductivity type.
Claim 4
Dependent Claim
35 words
The method of claim 2 wherein said diffusion of said second conductivity type forming said fourth region is patterned to form at least one laterally developed semiconductor device complementary to said vertically developed semiconductor devices.
Claim 5
Dependent Claim
39 words
The method of claim 2 wherein said diffusion of said second conductivity type forming said fourth region is patterned to form at least one laterally developed semiconductor device in said third region, complementary to said vertically developed semiconductor devices.
Claim 6
Dependent Claim
61 words
The method of claim 2 wherein said diffusion of said second conductivity type forming said fourth region is patterned to provide two laterally displaced regions of said second conductivity type, between which a portion of said second region of said first conductivity type is interposed, to form at least one laterally developed semiconductor device complementary to said vertically developed semiconductor devices.
Claim 7
Dependent Claim
80 words
The method of claim 5 wherein said diffusion of said second conductivity type forming said fourth region is patterned to provide two laterally displaced regions of said second conductivity type, one lying over said third region and the other lying over said second region to form an emitter and collector of said laterally developed semiconductor devices respectively, a base thereof including portions of said second and third regions of said first conductivity type, forming a graded base for improved performance.
Claim 8
Dependent Claim
63 words
The method of claim 5 wherein the provided substrate has a two layer second region, said third and fourth regions being formed in the upper layer, the lower layer being of a higher impurity level than the upper layer to improve the high voltage performance of the vertically developed devices and reduce the leakage and increase the gain of the horizontally developed devices.
Claim 9
Dependent Claim
21 words
The method of claim 5 wherein said first conductivity type is N type and said second conductivity type is P type.
Claim 10
Dependent Claim
55 words
The method of claim 2 wherein said diffusion of said second conductivity type forming said fourth region is patterned to form at least one laterally developed semiconductor device, the base thereof including a portion of said third region and a portion of said second region, said device being complementary to said vertically developed semiconductor devices.
Claim 11
Dependent Claim
47 words
The method of claim 2 wherein a ring of said second conductivity type is formed around said vertically developed devices in said second region, positioned for contact with the diffusion of step C, for enhancing high voltage performance, said ring formation occurring between steps B and C.
Claim 12
Dependent Claim
26 words
The method of claim 10 wherein said ring is formed by diffusing an impurity of said second conductivity type to a depth exceeding said third region.
Claim 13
Dependent Claim
30 words
The method of claim 10 wherein said ring is formed by implanting an impurity of said second conductivity type to a depth comparable to the depth of said fourth region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-09 | 1988-04-09 | 1988-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-09 | 1992-04-09 | 1992-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-09 | 1996-04-09 | 1996-10-09 | $7700.00 | Window Closed / Lapsed |