US4591894A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having a plurality of CMOS I/O cells located at the periphery of the chip arranged in a direction perpendicular to the sides of the chip
Assignee: Toshiba Corp
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Filing: 1983-01-05
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Granted: 1986-05-27
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Expires: 2003-01-05
Abstract
Abstract A semiconductor device comprises a gate array portion formed in the central portion of a chip, and a number of CMOS input/output cells arranged at the peripheral portion of the chip. Each input/output cell consists of a bonding pad, a p-channel MOS region and an n-channel MOS region, and extends inward from the side of the chip in a direction perpendicular to the side of the chip.
Inventors
- 👤 Susumu Kawakami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:14
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10D; H10D84/00; H10D84/90; H10D84/998; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10W72/50; H10W72/551; H10W72/552; H10W72/5524; Y; Y10; Y10S; Y10S257/00; Y10S257/923
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
152 words
A MOS gate array comprising: a semiconductor substrate of a first conductivity; an integrated circuit located in the center of said semiconductor substrate; a plurality of lead wires; and a plurality of CMOS input/output cells located along the peripheral portion of said semiconductor substrate, wherein said CMOS input/output cells are connected to said integrated circuit and each of said CMOS input/output cells includes a bonding pad located along the peripheral portion of said semiconductor substrate and connected to one of said plurality of lead wires, a first MOS region of a first channel type located adjacent to said bonding pad, and inward from said bonding pad and the edge of said semiconductor substrate in a perpendicular direction, and a second MOS region of a second channel type located adjacent to said first MOS region, and inward from said first MOS region and the edge of said semiconductor substrate in a perpendicular direction.
Claim 2
Dependent Claim
152 words
A MOS gate array comprising: a semiconductor substrate of a first conductivity; an integrated circuit located in the center of said semiconductor substrate; a plurality of lead wires; and a plurality of CMOS input/output cells located along the peripheral portion of said semiconductor substrate, wherein said CMOS input/output cells are connected to said integrated circuit and each of said CMOS input/output cells includes a bonding pad located along the peripheral portion of said semiconductor substrate and connected to one of said plurality of lead wires, a first MOS region of a first channel type located adjacent to said bonding pad, and inward from said bonding pad and the edge of said semiconductor substrate in a perpendicular direction, and a second MOS region of a second channel type located adjacent to said first MOS region, and inward from said first MOS region and the edge of said semiconductor substrate in a perpendicular direction.
Claim 3
Dependent Claim
52 words
The semiconductor device according to claim 1, wherein each of the first and second channel type MOS regions is divided into an active element region and a passive element region, and the first and second channel type passive element regions are sandwiched between the first and second channel type active element regions.
Claim 4
Dependent Claim
23 words
The semiconductor device according to claim 1, wherein the first channel type MOS region partly extends along the side of the bonding pad.
Claim 5
Dependent Claim
51 words
The semiconductor device according to claim 1, wherein said first and second MOS regions include an output buffer, an input buffer, an input protective circuit, a pull-up resistor and a pull-down resistor, which are coupled within said first and second MOS regions and to said integrated circuit and said bonding pad.
Claim 6
Dependent Claim
115 words
A semiconductor device, comprising: a chip of N-type semiconductor material having a linear edge and a peripheral area adjacent to one edge of said chip; a plurality of discrete input/output cells formed along said peripheral area of said chip with said cells being spaced from said one edge of said chip, each of said cells having active and passive regions extending along spaced lines in a parallel relation to said edge of said chip; a plurality of bonding pads mounted on said chip between said cells and said one edge of said chip; and said bonding pads and said regions of said cell being aligned along lines running perpendicular to said edge of said chip.
Claim 7
Dependent Claim
115 words
A semiconductor device, comprising: a chip of N-type semiconductor material having a linear edge and a peripheral area adjacent to one edge of said chip; a plurality of discrete input/output cells formed along said peripheral area of said chip with said cells being spaced from said one edge of said chip, each of said cells having active and passive regions extending along spaced lines in a parallel relation to said edge of said chip; a plurality of bonding pads mounted on said chip between said cells and said one edge of said chip; and said bonding pads and said regions of said cell being aligned along lines running perpendicular to said edge of said chip.
Claim 8
Dependent Claim
116 words
A MOS gate array comprising: a semiconductor substrate of a first conductivity; an integrated circuit located in said semiconductor substrate; and a plurality of CMOS input/output cells located along a peripheral portion of said semiconductor substrate, wherein said CMOS input/output cells include a bonding pad located along the peripheral portion of said semiconductor substrate, a first MOS region of a first channel type located adjacent to and inward from said bonding pad and in a perpendicular direction to the edge of said semiconductor substrate, and a second MOS region of a second channel type located adjacent to and inward from said first MOS region and in a perpendicular direction to the edge of said semiconductor substrate.
Claim 9
Dependent Claim
116 words
A MOS gate array comprising: a semiconductor substrate of a first conductivity; an integrated circuit located in said semiconductor substrate; and a plurality of CMOS input/output cells located along a peripheral portion of said semiconductor substrate, wherein said CMOS input/output cells include a bonding pad located along the peripheral portion of said semiconductor substrate, a first MOS region of a first channel type located adjacent to and inward from said bonding pad and in a perpendicular direction to the edge of said semiconductor substrate, and a second MOS region of a second channel type located adjacent to and inward from said first MOS region and in a perpendicular direction to the edge of said semiconductor substrate.
Claim 10
Dependent Claim
133 words
A MOS gate array comprising: a semiconductor substrate of a first conductivity; an integrated circuit located in said semiconductor substrate; and a plurality of CMOS input/output cells located along a peripheral portion of said semiconductor substrate, wherein said CMOS input/output cells include a bonding pad located along the peripheral portion of said semiconductor substrate, a first MOS region of a first channel type located adjacent to and inward from said bonding pad and in a perpendicular direction to the edge of said semiconductor substrate wherein a porton of said first MOS region partially extends along the side of said bonding pad, and a second MOS region of a second channel type located adjacent to and inward from said first MOS region and in a perpendicular direction to the edge of said semiconductor substrate.
Claim 11
Dependent Claim
133 words
A MOS gate array comprising: a semiconductor substrate of a first conductivity; an integrated circuit located in said semiconductor substrate; and a plurality of CMOS input/output cells located along a peripheral portion of said semiconductor substrate, wherein said CMOS input/output cells include a bonding pad located along the peripheral portion of said semiconductor substrate, a first MOS region of a first channel type located adjacent to and inward from said bonding pad and in a perpendicular direction to the edge of said semiconductor substrate wherein a porton of said first MOS region partially extends along the side of said bonding pad, and a second MOS region of a second channel type located adjacent to and inward from said first MOS region and in a perpendicular direction to the edge of said semiconductor substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-26 | 1989-11-25 | 1990-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-26 | 1993-11-25 | 1994-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-26 | 1997-11-25 | 1998-05-27 | $7700.00 | Window Closed / Lapsed |