US4503448A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit device with a high tolerance against abnormally high input voltage
Assignee: Fujitsu Ltd
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Filing: 1984-06-28
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Granted: 1985-03-05
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Expires: 2004-06-28
Abstract
Abstract A semiconductor integrated device with a high tolerance against abnormally high input voltages comprises a first MIS transistor at the input stage and a second MIS transistor of the internal elements of the device. The source of the first MIS transistor is connected to an input electrode. The drain of the first MIS transistor is connected to the gate of the second MIS transistor. The source region of the first MIS transistor comprises phosphoric atoms. The other diffusion regions comprise arsenic atoms. Therefore, the depth of the source region of the first MIS transistor is greater than the other diffusion region. In addition, the source region of the first MIS transistor has a considerable gradient with regard to the concentration of the phosphoric atoms. As a result, the depletion layer between the source region of the first MIS transistor and the semiconductor substrate is broader than in the other region. Consequently, a high tolerance against abnormal high input voltages is obtained.
Inventors
- 👤 Kiyoshi Miyasaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:49
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/8312; H10D89/00; H10D89/60; H10D89/601; H10D84/8311; H10D84/8314
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
325 words
A semiconductor integrated device having a high tolerance against abnormally high input voltages, comprising: a semiconductor substrate having a first conductivity type; an input electrode formed on said semiconductor substrate; an input stage of said semiconductor integrated device formed on said semiconductor substrate and including a first MIS transistor comprising a gate insulator layer, a first gate electrode, and a first source region and a first drain region each having a second conductivity type being the opposite of said first conductivity type, said first source region or said first drain region being electrically connected to said input electrode; an internal circuit of said semiconductor integrated device formed on said semiconductor substrate and including a second MIS transistor comprising a second gate electrode, a second source region, and a second drain region, each of said second source region and said second drain region having said second conductivity type, said second gate electrode being electrically connected to said first source region or said first drain region not connected to said input electrode; and another internal circuit of said semiconductor device operatively connected to said first gate electrode; said first source region or said first drain region connected to said input electrode has a depth greater than the depth of said second source or drain region, has a depth greater than said first source region or said first drain region not connected to said input electrode, and has an impurity concentration varying in a first direction perpendicular to the surface of said semiconductor substrate from a first concentration at the surface of said semiconductor substrate to a second concentration lower than said first concentration and at respective levels along said first direction being substantially uniform throughout said first source or drain region in a direction parallel to the surface to the surface of said semiconductor substrate, whereby said first gate insulation layer is prevented from destruction due to said abnormally high input voltages applied to said input electrode.
Claim 2
Dependent Claim
325 words
A semiconductor integrated device having a high tolerance against abnormally high input voltages, comprising: a semiconductor substrate having a first conductivity type; an input electrode formed on said semiconductor substrate; an input stage of said semiconductor integrated device formed on said semiconductor substrate and including a first MIS transistor comprising a gate insulator layer, a first gate electrode, and a first source region and a first drain region each having a second conductivity type being the opposite of said first conductivity type, said first source region or said first drain region being electrically connected to said input electrode; an internal circuit of said semiconductor integrated device formed on said semiconductor substrate and including a second MIS transistor comprising a second gate electrode, a second source region, and a second drain region, each of said second source region and said second drain region having said second conductivity type, said second gate electrode being electrically connected to said first source region or said first drain region not connected to said input electrode; and another internal circuit of said semiconductor device operatively connected to said first gate electrode; said first source region or said first drain region connected to said input electrode has a depth greater than the depth of said second source or drain region, has a depth greater than said first source region or said first drain region not connected to said input electrode, and has an impurity concentration varying in a first direction perpendicular to the surface of said semiconductor substrate from a first concentration at the surface of said semiconductor substrate to a second concentration lower than said first concentration and at respective levels along said first direction being substantially uniform throughout said first source or drain region in a direction parallel to the surface to the surface of said semiconductor substrate, whereby said first gate insulation layer is prevented from destruction due to said abnormally high input voltages applied to said input electrode.
Claim 3
Dependent Claim
90 words
A semiconductor integrated device as set forth in claim 1, further including: a resistor comprising a diffusion region having said second conductivity type and arranged between said input electrode and said first source or drain region connected to said input electrode, the tolerance voltage of said first source or said first drain region not connected to said input electrode, and the tolerance voltage between said diffusion region and said semiconductor substrate being made lower than the tolerance voltage of said first source or drain region connected to said input electrode.
Claim 4
Dependent Claim
58 words
A semiconductor integrated device as set forth in claim 1, wherein, said first source or first drain region connected to said input electrode is doped with phosphoric atoms, whereas, said second source region, said second drain region, and said first source region or said first drain region not connected to said input electrode is doped with arsenic ions.
Claim 5
Dependent Claim
19 words
A semiconductor integrated device as set forth in claim 2, wherein said diffusion region is doped with arsenic ions.
Claim 6
Dependent Claim
45 words
A semiconductor integrated device as set forth in claim 4, wherein, said input electrode comprises a first electrical contact to an end of said diffusion region, and said first source or first drain region is operatively connected to the other end of said diffusion region.
Claim 7
Dependent Claim
58 words
A semiconductor integrated device as set forth in claim 2, wherein, said first source or drain region connected to said input electrode is doped with phosphoric atoms, whereas, said second source region and said second drain region, and said first source region or said first drain region not connected to said input electrode is doped with arsenic atoms.
Claim 8
Dependent Claim
53 words
A semiconductor integrated device as set forth in claims 1, 2, 3, 4, 5 or 6, wherein, the depth of said first source or drain region connected to said input electrode is more than one micrometer, and the maximum depth of said second source region and said second drain region is 0.5 micrometers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1988-03-04 | 1988-09-03 | 1989-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-04 | 1992-09-03 | 1993-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-04 | 1996-09-03 | 1997-03-05 | $7700.00 | Window Closed / Lapsed |