Over voltage protective device and circuits for insulated gate transistors

Claim 2

A process for fabricating a semiconductor device comprising the steps of: a. forming an insulating layer on a planar surface of a semiconductor substrate of a first type and degree of conductivity; b. opening a hole in said insulating layer and diffusing doping impurities therethrough into said substrate to form a first region of a second type and higher degree of conductivity with its p/n metallurgical junction having a first profile with a first radius of curvature intersecting said planar surface; c. forming a second region of a first type and equal or higher degree of conductivity in said first region, contiguous with the substrate and forming a sharp profile in said first profile of said p/n metallurgical junction, having a second radius of curvature less than said first radius of curvature; d. said first region having a junction breakdown voltage determined by said sharp profile in said metallurgical p/n junction, and; e. attaching an electrode to said first region.

Claim 3

The process of claim 1 wherein the second region is formed by an ion implant.

Claim 4

The process of claim 2 wherein a gettering layer is formed over the insulating layer after ion implantation.

Claim 5

The process of claim 1 wherein the second region is formed by implanting through a thin insulating layer.

Claim 6

The process of claim 1 wherein said second region is formed by ion implanting through a thick insulating layer.

Claim 7

The process of claim 1 wherein the area of the first conductivity type along the p/n junction extends into the region of second conductivity type.

Claim 8

A process for fabricating an over voltage protective device comprising the steps of: a. forming an insulating layer on a planar surface of a semiconductor substrate of a first type and degree of conductivity; b. opening two holes in said insulating layer and diffusing doping impurities therethrough into said substrate to form first and second regions of a second type and higher degree of conductivity with their p/n metallurgical junctions having first profiles with a first radius of curvature intersecting said planar surface; c. reforming said insulating layer in and outside said two holes with a relatively thick insulating layer; d. opening three holes in said thick insulating layer, the first of said holes disposed at least over a portion of said intersection between the planar surface and said first profile of the p/n junction of said first region, the second of said holes disposed over said first region and spaced from said first hole and the third hole disposed over said second region; e. reforming the insulating layer in each one of said three holes to a preselected thin thickness; f. forming a third region of a first type and of equal or higher degree of conductivity in said first region, contiguous with the substrate and forming a sharp profile in said first profile of said p/n metallurgical junction, having a second radius of curvature less than said first radius of curvature; g. removing said thin insulating layer from said second and third holes, h. forming a first electrode on said thin insulating layer covering said first hole and extending over said thick insulating layer to cover said third hole to make electrical contact with said second region, and; i. forming a second electrode covering said second hole to make electrical contact with said first region and extending over said thick insulating layer to form the gate electrodes of the insulated gate transistors to be protected against electrostatic discharges applied between this second electrode and said semiconductor substrate.

Claim 9

A process for fabricating an over voltage protective device comprising the steps of: a. forming an insulating layer on a planar surface of a semiconductor substrate of a first type and degree of conductivity; b. opening two holes in said insulating layer and diffusing doping impurities therethrough into said substrate to form first and second regions of a second type and higher degree of conductivity with their p/n metallurgical junctions having first profiles with a first radius of curvature intersecting said planar surface; c. reforming said insulating layer in and outside said two holes with a relatively thick insulating layer; d. opening three holes in said thick insulating layer, the first of said holes disposed at least over a portion of said intersection between the planar surface and said first profile of the p/n junction of said first region, the second of said holes disposed over said first region and spaced from said first hole and the third hole disposed over said second region; e. reforming the insulating layer in each one of said three holes to a preselected thin thickness; f. forming a third region of a first type and of equal or higher degree of conductivity in said first region, contiguous with the substrate and forming a sharp profile in said first profile of said p/n metallurgical junction, having a second radius of curvature less than said first radius of curvature; g. removing said thin insulating layer from said second and third holes, h. forming a first electrode on said thin insulating layer covering said first hole and extending over said thick insulating layer to cover said third hole to make electrical contact with said second region, and; i. forming a second electrode covering said second hole to make electrical contact with said first region and extending over said thick insulating layer to form the gate electrodes of the insulated gate transistors to be protected against electrostatic discharges applied between this second electrode and said semiconductor substrate.

Claim 10

The process of claim 7 wherein said region of first conductivity type is formed by ion implantation through said insulating layer of preselected thickness.

Claim 11

A process for fabricating an over voltage protective device comprising the steps of: a. forming an insulating layer on a planar surface of a semiconductor substrate of a first type and degree of conductivity; b. opening two holes in said insulating layer and diffusing doping impurities therethrough into said substrate to form first and second regions of a second type and higher degree of conductivity with their p/n metallurgical junctions having profiles with a radius of curvature intersecting said planar surface; c. forming said insulating layer in and outside said two holes with a relatively thick insulating layer; d. opening three holes in said thick insulating layer, the first of said holes disposed at least over a portion of said intersection between the planar surface and said profile of the p/n junction of said first region, the second of said holes disposed over said first region and spaced from said first hole and the third hole disposed over said second region; e. reforming the insulating layer in each one of said three holes to a preselected thin thickness; f. removing said thin insulating layer from said second and third holes; g. forming a first electrode on said thin insulating layer covering said first hole and extending over said thick insulating layer to cover said third hole and make electrical contact with said second region, and; h. forming a second electrode covering said second hole to make electrical contact with said first hole and extending over said thick insulating layer to form the gate electrodes of the insulated gate transistors to be protected against electrostatic discharges applied between this second electrode and said semiconductor substrate.

Claim 12

A process for fabricating an over voltage protective device comprising the steps of: a. forming an insulating layer on a planar surface of a semiconductor substrate of a first type and degree of conductivity; b. opening two holes in said insulating layer and diffusing doping impurities therethrough into said substrate to form first and second regions of a second type and higher degree of conductivity with their p/n metallurgical junctions having profiles with a radius of curvature intersecting said planar surface; c. forming said insulating layer in and outside said two holes with a relatively thick insulating layer; d. opening three holes in said thick insulating layer, the first of said holes disposed at least over a portion of said intersection between the planar surface and said profile of the p/n junction of said first region, the second of said holes disposed over said first region and spaced from said first hole and the third hole disposed over said second region; e. reforming the insulating layer in each one of said three holes to a preselected thin thickness; f. removing said thin insulating layer from said second and third holes; g. forming a first electrode on said thin insulating layer covering said first hole and extending over said thick insulating layer to cover said third hole and make electrical contact with said second region, and; h. forming a second electrode covering said second hole to make electrical contact with said first hole and extending over said thick insulating layer to form the gate electrodes of the insulated gate transistors to be protected against electrostatic discharges applied between this second electrode and said semiconductor substrate.