Abstract A circuit is provided for protecting an insulated gate fieldeffect transistor (IGFET) circuit from damage caused by spurious, high voltage input resulting primarily from static charge. The protection circuit is another IGFET whose drain is connected to the gate of the IGFET to be protected and whose source is connected to a common terminal. Also included in the protection circuit is a p-n junction. The gate of the protection circuit IGFET is connected to the p-n junction whose other terminal is connected to the common terminal and which is connected to be reverse biased. The protection circuit IGFET goes into an avalanche condition when a spurious signal of a polarity to cause a reverse bias is of sufficient amplitude to start an injection of carriers from the drain to the gate. The avalanche condition is maintained until the drain voltage drops below the avalanche maintenance value, at which time the p-n junction permits the charge built up on the gate as a result of the avalanche, to leak to the substrate.
An integrated, input protection circuit, formed upon a substrate, having input means connected to the gate of at least one main circuit, insulated gate field-effect transistor to be protected from spurious high amplitude voltage signals comprising: a a protection circuit insulated gate field-effect transistor having a gate, and having a drain connected to the input means and a source connected to a common reference for injection of carriers from the drain to the gate in an avalanche mode to charge the gate when a spurious signal of a reverse bias polarity is received; and b a p-n junction connected between the gate of the protection circuit insulated gate field-effect transistor and the common reference in a reverse bias direction, for providing impedance in the gate circuit of the protection circuit insulated gate field-effect transistor and for providing a leakage path for the charge on the gate after the spurious signal decreases to sTop the avalanche mode.
Claim 2
Dependent Claim
156 words
An integrated, input protection circuit, formed upon a substrate, having input means connected to the gate of at least one main circuit, insulated gate field-effect transistor to be protected from spurious high amplitude voltage signals comprising: a a protection circuit insulated gate field-effect transistor having a gate, and having a drain connected to the input means and a source connected to a common reference for injection of carriers from the drain to the gate in an avalanche mode to charge the gate when a spurious signal of a reverse bias polarity is received; and b a p-n junction connected between the gate of the protection circuit insulated gate field-effect transistor and the common reference in a reverse bias direction, for providing impedance in the gate circuit of the protection circuit insulated gate field-effect transistor and for providing a leakage path for the charge on the gate after the spurious signal decreases to sTop the avalanche mode.
Claim 3
Dependent Claim
20 words
The circuit of claim 1 wherein the main circuit and the protection circuit insulated gate field-effect transistors are MOS devices.
Claim 4
Dependent Claim
19 words
The circuit of claim 1 wherein the protection circuit insulated gate field-effect transistor is of the p-channel conductivity type.
Claim 5
Dependent Claim
17 words
The circuit of claim 2 wherein the protection circuit MOS device is of the p-channel conductivity type.