Structure for shallow junction MOS circuits

Claim 2

An MOS integrated circuit including source and drain regions (20 and 21) of one conductivity type formed in one major surface of a semiconductor body (10) of opposite conductivity type so as to form p-n junctions therein and a structure for making electrical contact to portions of the circuit comprising an insulating layer (23) formed over the circuit and including windows (24 and 25) formed therein exposing the portions to be contacted, a layer (26) of polycrystalline silicon selectively formed over said insulating layer so as to form a continuous coating over the side walls of said windows, and a layer of metal (28 and 29) formed over said polycrystalline silicon layer CHARACTERIZED IN THAT the junction depths of the source and drain regions are 0.40 μm or less, the side walls of the windows are steep with sharp edges, the layer of metal is essentially discontinuous at the side walls, and the polycrystalline silicon layer provides a low resistance to current conduction in the areas of the side walls.

Claim 3

The circuit according to claim 1 wherein the metal layer comprises aluminum.

Claim 4

The circuit according to claim 1 wherein the metal layer has a thickness of 0.10-2.0 μm over the portions of the polycrystalline silicon layer outside the areas of the side walls and a thickness of 0-1/2 of said thickness over the areas of the side walls.

Claim 5

The circuit according to claim 1 wherein the resistivity of the polycrystalline silicon layer is 50Ω/ or less.

Claim 6

The circuit according to claim 1 wherein the thickness of the polycrystalline silicon layer is within the range of 0.10 μm-1.0 μm.

Claim 7

The circuit according to claim 1 wherein the insulator comprises a phosphosilicate glass.

Claim 8

An MOS integrated circuit including source and drain regions (20 and 21) of one conductivity type formed in one major surface of a semiconductor body (10) of opposite conductivity type so as to form p-n junctions therein and a structure for making electrical contact to portions of the circuit comprising an insulating layer (23) formed over the circuit and including windows (24 and 25) formed therein exposing the portions to be contacted, a layer (26) of polycrystalline silicon selectively formed over said insulating layer so as to form a continuous coating over the side walls of said windows, and a layer of metal (28 and 29) formed over said polycrystalline silicon layer CHARACTERIZED IN THAT the junction depths of the source and drain regions are 0.40 μm or less, the side walls of the windows are essentially vertical with sharp edges, and the layer of metal is discontinuous at the side walls so that current conduction is provided by the polycrystalline silicon layer in the areas of the side walls.

Claim 9

An MOS integrated circuit including source and drain regions (20 and 21) of one conductivity type formed in one major surface of a semiconductor body (10) of opposite conductivity type so as to form p-n junctions therein and a structure for making electrical contact to portions of the circuit comprising an insulating layer (23) formed over the circuit and including windows (24 and 25) formed therein exposing the portions to be contacted, a layer (26) of polycrystalline silicon selectively formed over said insulating layer so as to form a continuous coating over the side walls of said windows, and a layer of metal (28 and 29) formed over said polycrystalline silicon layer CHARACTERIZED IN THAT the junction depths of the source and drain regions are 0.40 μm or less, the side walls of the windows are essentially vertical with sharp edges, and the layer of metal is discontinuous at the side walls so that current conduction is provided by the polycrystalline silicon layer in the areas of the side walls.

Claim 10

An MOS integrated circuit including source and drain regions (20 and 21, respectively) of one conductivity type formed in one major surface of a semiconductor body of opposite conductivity type (10) so as to form p-n junctions therein and further including a structure for making electrical contact to portions of the circuit including said source and drain regions comprising a phosphosilicate glass layer (23) formed over the circuit and including windows (24 and 25) formed therein exposing the portions to be contacted, a layer (26) of polycrystalline silicon selectively formed over said insulating layer so as to form a continuous coating over the side walls of said windows and over the exposed portions, and a layer of metal (28 and 29) comprising aluminum formed over said polycrystalline layer CHARACTERIZED IN THAT the junction depths of the source and drain regions are 0.40 μm or less, the side walls of the windows are essentially vertical with sharp edges, the layer of metal is discontinuous at the side walls, and the polycrystalline silicon layer is formed with a thickness of 0.10 μm-1.0 μm and a resistivity of 50Ω / or less so that current conduction is provided by the polycrystalline silicon layer in the areas of the side walls.

Claim 11

An MOS integrated circuit including source and drain regions (20 and 21, respectively) of one conductivity type formed in one major surface of a semiconductor body of opposite conductivity type (10) so as to form p-n junctions therein and further including a structure for making electrical contact to portions of the circuit including said source and drain regions comprising a phosphosilicate glass layer (23) formed over the circuit and including windows (24 and 25) formed therein exposing the portions to be contacted, a layer (26) of polycrystalline silicon selectively formed over said insulating layer so as to form a continuous coating over the side walls of said windows and over the exposed portions, and a layer of metal (28 and 29) comprising aluminum formed over said polycrystalline layer CHARACTERIZED IN THAT the junction depths of the source and drain regions are 0.40 μm or less, the side walls of the windows are essentially vertical with sharp edges, the layer of metal is discontinuous at the side walls, and the polycrystalline silicon layer is formed with a thickness of 0.10 μm-1.0 μm and a resistivity of 50Ω / or less so that current conduction is provided by the polycrystalline silicon layer in the areas of the side walls.

Claim 12

The circuit according to claims 1, 7 or 8 wherein the resistance provided by the polycrystalline silicon layer in the areas of the side walls is less than one-half of the source to drain sheet resistance of the MOS device being contacted.

Claim 13

The circuit according to claims 1, 7 or 8 wherein the thickness of the insulating layer is within the range 0.50 to 2.0 microns.