US4141023A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Field effect transistor having a linear attenuation characteristic and an improved distortion factor with multiple gate drain contacts
Assignee: Sony Corp
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Filing: 1977-10-26
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Granted: 1979-02-20
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Expires: 1997-10-26
Abstract
Abstract A field effect transistor having two electrodes and distributed resistance therebetween is disclosed. This device is used as an attenuator when a main signal is applied across one drain electrode and a source and a control voltage is applied between a gate and the source. The output is derived from the other drain electrode.
Inventors
- 👤 Takaaki Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:11
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H03; H03G; H03G1/00; H03G1/0005; H03G1/0035; H03G1/007; H03H; H03H11/00; H03H11/02; H03H11/24; H03H11/245; H10D99/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
239 words
A field effect transistor comprising: a semiconductor substrate of one conductivity type; source and drain regions of opposite conductivity type respectively extending into said substrate from one surface thereof; a channel region formed between said source and drain regions, means connected to said source and drain regions for generating a channel current therebetween; said drain and source regions extending transversely of said channel region and having edges spaced on opposite ends of said channel region and said edges located and spaced apart transversely of said channel current, first and second drain electrodes electrically connected to said edges of said drain region; said drain region having a resistance between said edges which is higher than the resistance between the edges of said source region; an insulating layer formed on said channel region; a gate region formed on said insulating layer; a first gate electrode electrically connected to said gate region; a source electrode electrically connected to said source region; wherein said gate region is formed of electrically resistive material; including a second gate electrode, said first and second gate electrodes electrically connected to said gate region at points spaced apart transversely to said current; and wherein said field effect transistor is a variable impedance means including an input circuit connected to said first drain and source electrodes, an output circuit connected to said second drain and source electrodes, and a control circuit connected to said first and second gate electrodes.
Claim 2
Dependent Claim
239 words
A field effect transistor comprising: a semiconductor substrate of one conductivity type; source and drain regions of opposite conductivity type respectively extending into said substrate from one surface thereof; a channel region formed between said source and drain regions, means connected to said source and drain regions for generating a channel current therebetween; said drain and source regions extending transversely of said channel region and having edges spaced on opposite ends of said channel region and said edges located and spaced apart transversely of said channel current, first and second drain electrodes electrically connected to said edges of said drain region; said drain region having a resistance between said edges which is higher than the resistance between the edges of said source region; an insulating layer formed on said channel region; a gate region formed on said insulating layer; a first gate electrode electrically connected to said gate region; a source electrode electrically connected to said source region; wherein said gate region is formed of electrically resistive material; including a second gate electrode, said first and second gate electrodes electrically connected to said gate region at points spaced apart transversely to said current; and wherein said field effect transistor is a variable impedance means including an input circuit connected to said first drain and source electrodes, an output circuit connected to said second drain and source electrodes, and a control circuit connected to said first and second gate electrodes.
Claim 3
Dependent Claim
41 words
A field effect transistor according to claim 1 in which different control voltages are applied to said first and second gate electrodes so that the input impedance to said input circuit is higher than the output impedance to said output circuit.
Claim 4
Dependent Claim
186 words
A field effect transistor comprising: a semiconductor substrate of one conductivity type; source and drain regions of opposite conductivity type respectively extending into said substrate from one surface thereof; a channel region formed between said source and drain regions, means connected to said source and drain region for generating a channel current therebetween; said drain and source regions having edges spaced on opposite ends of said channel region and said edges located and spaced apart transversely of said channel current, first and second drain electrodes electrically connected to said edges of said drain region; said drain region having a resistance between said edges which is higher than the resistance between the edges of said source region; an insulating layer formed on said channel region; a gate region formed on said insulating layer; a first gate electrode electrically connected to said gate region; a source electrode electrically connected to said source region; wherein said gate region is formed of electrically resistive material; and including second and third gate electrodes, said first, second and third gate electrodes respectively mounted adjacent said source, first drain and second drain electrodes.
Claim 5
Dependent Claim
186 words
A field effect transistor comprising: a semiconductor substrate of one conductivity type; source and drain regions of opposite conductivity type respectively extending into said substrate from one surface thereof; a channel region formed between said source and drain regions, means connected to said source and drain region for generating a channel current therebetween; said drain and source regions having edges spaced on opposite ends of said channel region and said edges located and spaced apart transversely of said channel current, first and second drain electrodes electrically connected to said edges of said drain region; said drain region having a resistance between said edges which is higher than the resistance between the edges of said source region; an insulating layer formed on said channel region; a gate region formed on said insulating layer; a first gate electrode electrically connected to said gate region; a source electrode electrically connected to said source region; wherein said gate region is formed of electrically resistive material; and including second and third gate electrodes, said first, second and third gate electrodes respectively mounted adjacent said source, first drain and second drain electrodes.
Claim 6
Dependent Claim
32 words
A field effect transistor according to claim 3 further including at least one further drain electrode electrically connected to said drain region at a point between said first and second drain electrodes.
Claim 7
Dependent Claim
62 words
A field effect transistor according to claim 3 where said transistor is a variable impedance means, including an input circuit connected to said first drain and source electrodes, an output circuit connected to said second drain and source electrodes, a control circuit connected to said first gate electrode, and capacitance means coupled between said drain region and said gate region corresponding thereto.
Claim 8
Dependent Claim
207 words
A field effect transistor comprising: a semiconductor substrate of one conductivity type; a source region and a single drain region with multiple electrodes of opposite conductivity type respectively extending into said substrate from one surface thereof; a channel region formed between said source and drain regions, means connected to said source and drain region for generating a channel current therebetween, said drain and source regions extending transversely of said channel region and having edges spaced on opposite ends of said channel region and said edges located and spaced apart transversely of said channel current, first and second drain electrodes electrically connected to said edges of said single drain region; said drain region having a resistance between said edges which is higher than the resistance between the edges of said source region; an insulating layer formed on said channel region; a gate region formed on said insulating layer; a first gate electrode electrically connected to said gate region; a source electrode electrically connected to said source region; wherein the resistivity of said gate region is higher than that of said gate electrode, and including a second gate electrode, said first and second gate electrodes electrically connected to said gate region at points spaced apart transversely to said current.
Claim 9
Dependent Claim
207 words
A field effect transistor comprising: a semiconductor substrate of one conductivity type; a source region and a single drain region with multiple electrodes of opposite conductivity type respectively extending into said substrate from one surface thereof; a channel region formed between said source and drain regions, means connected to said source and drain region for generating a channel current therebetween, said drain and source regions extending transversely of said channel region and having edges spaced on opposite ends of said channel region and said edges located and spaced apart transversely of said channel current, first and second drain electrodes electrically connected to said edges of said single drain region; said drain region having a resistance between said edges which is higher than the resistance between the edges of said source region; an insulating layer formed on said channel region; a gate region formed on said insulating layer; a first gate electrode electrically connected to said gate region; a source electrode electrically connected to said source region; wherein the resistivity of said gate region is higher than that of said gate electrode, and including a second gate electrode, said first and second gate electrodes electrically connected to said gate region at points spaced apart transversely to said current.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-02-19 | 1982-08-21 | 1983-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-02-19 | 1986-08-21 | 1987-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-02-19 | 1990-08-21 | 1991-02-20 | $7700.00 | Window Closed / Lapsed |