Semiconductor device employing two-metal contact and polycrystalline isolation means

Claim 2

A semiconductor device according to claim 2, wherein said resistive means and said polycrystalline semiconductor layer comprise an integral layer of polycrystalline semiconductor material disposed over said coating and in said aperture.

Claim 3

A semiconductor device according to claim 3, wherein said first layer comprises a refractory metal.

Claim 4

A semiconductor device according to claim 4, wherein said second layer is selected from a group consisting of gold, silver, aluminum, and platinum.

Claim 5

In a semiconductor device of the type having a relatively high temperature operating area and a relatively low temperature operating area, a contact structure comprising: a first layer of a metal having relatively high temperature properties overlying and in electrical contact with said high temperature operating area; a second layer of a metal having relatively low temperature properties overlying and electrically isolated from said low temperature operating area; a polycrystalline semiconductor layer interposed between said first and second layers; termination means contacting said second layer; and wherein said first and second layers and said polycrystalline semiconductor layer define a current path between said termination means and said high temperature operating area.

Claim 6

A semiconductor device comprising in combination: a silicon body having a major surface; a silicon oxide coating overlying said surface, said coating having an aperture extending to said surface; a polycrystalline silicon layer disposed over said coating and in said aperture, said silicon layer having an impurity concentration of between 1019 and 1021 atoms/cm3; a refractory metal layer disposed on a first portion of said silicon layer; a second metal layer selected from the group consisting of gold, silver, aluminum, and platinum disposed on a second portion of said silicon layer; said second layer being spaced from said refractory layer by a third portion of said silicon layer which provides metallurgical isolation and a selective resistance between said two metal layers; and a terminal lead bonded to said second layer.

Claim 7

An improved overlay transistor of the type formed in a semiconductor body having a major surface, said transistor including a collector region therein which extends to said surface, a plurality of base regions extending into said collector region from said surface, a base conduction grid between adjacent base regions, an emitter region extending into each base region from said surface, an insulating coating overlying said surface and having a plurality of apertures each of which exposes one emitter region, said coating having a relatively thick portion adjacent said collector region and a relatively thin portion adjacent said base regions, wherein the improvement comprises: a polycrystalline semiconductor layer disposed over said thick and thin portions and contacting said emitter regions through said apertures; a refractory metal layer disposed only over that part of said semiconductor layer over said thin portion; a metal layer having low temperature prOperties spaced from said refractory layer and disposed over that part of said semiconductor layer over said thick portion; and a terminal lead bonded to said low temperature layer over said thick portion.