High temperature refractory metal contact assembly and multiple layer interconnect structure

Claim 2

An integrated circuit interconnection structure comprising. a silicon body having a surface, a first insulating layer having at least one aperture formed on the surface to expose portions of the surface of said silicon body, a refractory metal sandwich formed on the upper surface of portions of the insulating layer and at least one portion of the exposed body portion, and extending through at least one aperture to contact the silicon body, said sandwich including solely the combination of a silicon layer formed on a body portion and on the insulating layer, a refractory metal layer formed on the silicon layer and a second silicon layer formed on the upper surface of the refractory metal layer, a second insulating layer formed at least on portions of the upper surface of the refractory metal sandwich and on portions of the first insulating layer at least one opening formed in said second insulating layer at said portions to expose the underlying portion of the refractory metal sandwich, and a metal layer formed on the upper surface of portions of said second insulating layer and extending through at least one opening formed in the second insulating layer to contact said refractory metal sandwich.

Claim 3

A structure as in claim 1 wherein the additional metal layer has interconnecting segments which selectively form ohmic contacts with upper surface portions exposed by apertures and openings.

Claim 4

A structure as in claim 1 wherein the additional metal layer is selected from a group consisting of aluminum, gold or silver.

Claim 5

A structure as in claim 1 wherein first and second insulating layers include a silicon dioxide layer and a silicon nitride layer formed on the upper surface of the silicon dioxide layer.

Claim 6

A complementary MOS integrated circuit structure comprising, an N type silicon body having a surface, at least one N channel field effect transistor and at least one P channel field effect transistor, the N channel transistor including a P- region extending to the surface of the body, and spaced N+ regions formed within the P- region and extending to the surface, the P channel transistor including a pair of spaced P+ regions extending to the surface of the body, isolation rings extending to the surface of the body surrounding and isolating said transistors, a first insulating layer formed on the surface of the body, a refractory metal sandwich formed on the upper surface of the first insulating layer, said sandwich including solely the combination of a first silicon layer formed on the upper surface of the first insulating layer, a refractory metal layer formed on the first silicon layer, and a second silicon layer formed on the upper surface of the refractory metal layer, the refractory metal sandwich having one portion which overlies the body surface between the spaced P+ regions to form the P channel transistor gate, and another portion which overlies the body surface between the spaced N+ regions to form the N channel transistor gate, a second insulating layer formed on the upper surface of the refractory metal sandwich, openings in said insulating and refractory metal layers extending through said second insulating layer or through both of said insulating layers, and an additional metal layer formed on selected portions of the upper surface of the second insulating layer, and extending through said openings to selectively contact said refractory metal sandwich and said silicon body surface at predetermined locations.

Claim 7

A complementary MOS integrated circuit structure comprising, an N type silicon body having a surface, at least one N channel field effect transistor and at least one P channel field effect transistor, the N channel transistor including a P- region extending to the surface of the body, and spaced N+ regions formed within the P- region and extending to the surface, the P channel transistor including a pair of spaced P+ regions extending to the surface of the body, isolation rings extending to the surface of the body surrounding and isolating said transistors, a first insulating layer formed on the surface of the body, a refractory metal sandwich formed on the upper surface of the first insulating layer, said sandwich including solely the combination of a first silicon layer formed on the upper surface of the first insulating layer, a refractory metal layer formed on the first silicon layer, and a second silicon layer formed on the upper surface of the refractory metal layer, the refractory metal sandwich having one portion which overlies the body surface between the spaced P+ regions to form the P channel transistor gate, and another portion which overlies the body surface between the spaced N+ regions to form the N channel transistor gate, a second insulating layer formed on the upper surface of the refractory metal sandwich, openings in said insulating and refractory metal layers extending through said second insulating layer or through both of said insulating layers, and an additional metal layer formed on selected portions of the upper surface of the second insulating layer, and extending through said openings to selectively contact said refractory metal sandwich and said silicon body surface at predetermined locations.

Claim 8

A structure as in claim 5 wherein said refractory metal layer is selected from a group consisting of molybdenum, tungsten, platinum, nickel and palladium.

Claim 9

A structure as in claim 5 wherein said refractory metal layer is approximately 2000 to 5000 A thick.

Claim 10

A structure as in claim 5 wherein the additional metal layer is formed into interconnecting segments which selectively form ohmic contacts with the upper surface of portions of the body.

Claim 11

A structure as in claim 5 wherein first and second insulating layers include a silicon dioxide layer and a silicon nitride layer formed on the upper surface of the silicon dioxide layer.

Claim 12

A structure as in claim 5 wherein the isolation rings are N+ channel stops surrounding the P channel transistor and p+ channel stops surrounding the N channel transistor.

Claim 13

An integrated circuit comprising, a silicon body having a major surface, an insulated layer overlying said surface and including apertures extending to said surface. a first silicon layer overlying portions of said insulating layer, a refractory metal layer overlying said first silicon layer, a second silicon layer overlying said refractory metal layer, a second insulating layer overlying said second silicon layers, said second insulating layer including an aperture extending to said second silicon layer, a metal layer overlying said second insulating layer and extending through said apertures to contact said second silicon layer.

Claim 14

An integrated circuit comprising, a silicon body having a major surface, an insulated layer overlying said surface and including apertures extending to said surface. a first silicon layer overlying portions of said insulating layer, a refractory metal layer overlying said first silicon layer, a second silicon layer overlying said refractory metal layer, a second insulating layer overlying said second silicon layers, said second insulating layer including an aperture extending to said second silicon layer, a metal layer overlying said second insulating layer and extending through said apertures to contact said second silicon layer.

Claim 15

A structure as in claim 11 wherein said refractory metal layer is selected from a group consisting of molybdenum, tungsten, platinum, nickel and palladium.

Claim 16

A structure as in claim 11 wherein said refractory metal layer is between 2,000 to 5,000 angstroms thick.