US4172260A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Insulated gate field effect transistor with source field shield extending over multiple region channel
Assignee: Hitachi Ltd
•
Filing: 1977-11-21
•
Granted: 1979-10-23
•
Expires: 1997-11-21
Abstract
Abstract In an insulated gate field effect transistor having a source region and a drain region of the P-conductivity type which are disposed in surface portions of a semiconductor substrate of the N-conductivity type in a manner to be spaced apart from each other, a gate electrode being disposed through an insulating film on the substrate between the source region and the drain region, an insulated gate field effect transistor wherein said drain region is disposed apart from said gate electrode, two regions of an intermediate region and a high resistance region which are of the P-conductivity type and which successively extend from said drain region towards the side of said gate electrode are disposed in surface portions of the substrate situated between said drain region and said gate electrode, said intermediate region having an impurity concentration lower than that of said drain region, said high resistance region having an impurity concentration lower than that of said intermediate region, and a source electrode extends over and beyond said gate electrode and said high resistance region through said insulating film and terminates over said intermediate region.
Inventors
- 👤 Takeaki Okabe
- 👤 Isao Yoshida
- 👤 Shikayuki Ochi
- 👤 Hidefumi Itoh
- 👤 Masatomo Furumi
- 👤 Toru Toyabe
- 👤 Mineo Katsueda
- 👤 Yukio Shirota
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:29
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/111; H10D64/112; H10D30/00; H10D30/60; H10D30/601; H10D30/603
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
233 words
An insulated gate field effect transistor comprising: a semiconductor substrate of a first conductivity type; a source region of a second conductivity type, opposite said first conductivity type, disposed in a first surface portion of said substrate; a resistor region of said second conductivity type disposed in a second surface portion of said substrate spaced apart from said source region by a third surface portion of said substrate between; an intermediate region of said second conductivity type having an impurity concentration higher than that of said resistor region and disposed in a fourth surface portion of said substrate contiguous to said second surface portion; a drain region of said second conductivity type having an impurity concentration higher than that of said intermediate region and disposed in a fifth surface portion of said substrate contiguous to said fourth surface portion; a first insulating film disposed on said substrate between said source and resistor regions; a gate electrode disposed on said first insulating film; a second insulating film disposed on at least said gate electrode, said second surface portion, and said fourth surface portion; a drain electrode connected to said drain region; and a source electrode connected to said source region, extending on said second insulating film, covering said gate electrode, said resistor region, and a part of said intermediate region, so that one edge of said source electrode is located above said intermediate region.
Claim 2
Dependent Claim
233 words
An insulated gate field effect transistor comprising: a semiconductor substrate of a first conductivity type; a source region of a second conductivity type, opposite said first conductivity type, disposed in a first surface portion of said substrate; a resistor region of said second conductivity type disposed in a second surface portion of said substrate spaced apart from said source region by a third surface portion of said substrate between; an intermediate region of said second conductivity type having an impurity concentration higher than that of said resistor region and disposed in a fourth surface portion of said substrate contiguous to said second surface portion; a drain region of said second conductivity type having an impurity concentration higher than that of said intermediate region and disposed in a fifth surface portion of said substrate contiguous to said fourth surface portion; a first insulating film disposed on said substrate between said source and resistor regions; a gate electrode disposed on said first insulating film; a second insulating film disposed on at least said gate electrode, said second surface portion, and said fourth surface portion; a drain electrode connected to said drain region; and a source electrode connected to said source region, extending on said second insulating film, covering said gate electrode, said resistor region, and a part of said intermediate region, so that one edge of said source electrode is located above said intermediate region.
Claim 3
Dependent Claim
65 words
An insulated gate field effect transistor according to claim 1, wherein said second insulating film is further disposed on a part of said fifth surface portion, and said drain electrode extends on said second insulating film and covers a part of said drain region and a part of said intermediate region, so that one edge of said drain electrode is located above said intermediate region.
Claim 4
Dependent Claim
33 words
An insulated gate field effect transistor according to claim 1, wherein said fifth surface portion is including in said fourth surface portion, so that said drain region is disposed in said intermediate region.
Claim 5
Dependent Claim
33 words
An insulated gate field effect transistor according to claim 3, wherein a depth of said intermediate region in said substrate is greater than a depth of said drain region in said intermediate region.
Claim 6
Dependent Claim
34 words
An insulated gate field effect transistor according to claim 1, wherein said gate electrode, source electrode, and drain electrode are made of a material selected from the group consisting of metals and semiconductor materials.
Claim 7
Dependent Claim
74 words
An insulated gate field effect transistor according to claim 1, said first and second insulating films are made of a film selected from the group consisting of SiO 2 , Si 3 N 4 , Al 2 O 3 , SiO 2 /PbO(leadsilicate glass), SiO 2 /P 2 O 5 (phosphosilicate glass), SiO 2 /P 2 o 5 (boronsilicate glass) films, and double layer films formed of a combination of two of these films.
Claim 8
Dependent Claim
29 words
An insulated gate field effect transistor according to claim 1, wherein said semiconductor substrate is a semiconductor from the group consisting of semiconductors Si, Ge, GaAs, InP, and InSb.
Claim 9
Dependent Claim
27 words
An insulated gate field effect transistor according to claim 1, wherein an impurity concentration of said drain region is as same as that of said source region.
Claim 10
Dependent Claim
29 words
An insulated gate field effect transistor according to claim 8, wherein an impurity concentration of said intermediate region is lower than 10 -2 times that of said drain region.
Claim 11
Dependent Claim
30 words
An insulated gate field effect transistor according to claim 9, wherein a total impurity quantity of said resistor region is lower than 10 -1 times that of said intermediate region.
Claim 12
Dependent Claim
216 words
An insulated gate field effect transistor comprising: a semiconductor substrate of a first conductivity type; a source region of a second conductivity type, opposite said first conductivity type, disposed in a first surface portion of said substrate; a resistor region of said second conductivity type disposed in a second surface portion of said substrate spaced apart from said source region by a third surface portion of said substrate between; an intermediate region of said second conductivity type having an impurity concentration higher than that of said resistor region and disposed in a fourth surface portion of said substrate contiguous to said second surface portion; a drain region of said second conductivity type having an impurity concentration higher than that of said intermediate region and disposed in a fifth surface portion of said substrate contiguous to said fourth surface portion; a first insulating film disposed on said substrate between said source and resistor regions; a gate electrode disposed on said first insulating film; a drain electrode connected to said drain region; and a source electrode connected to said source region, extending over said gate electrode, said resistor region, and a part of said intermediate region, and electrically insulated by a insulating film therefrom, so that one edge of said source electrode is located above said intermediate region.
Claim 13
Dependent Claim
216 words
An insulated gate field effect transistor comprising: a semiconductor substrate of a first conductivity type; a source region of a second conductivity type, opposite said first conductivity type, disposed in a first surface portion of said substrate; a resistor region of said second conductivity type disposed in a second surface portion of said substrate spaced apart from said source region by a third surface portion of said substrate between; an intermediate region of said second conductivity type having an impurity concentration higher than that of said resistor region and disposed in a fourth surface portion of said substrate contiguous to said second surface portion; a drain region of said second conductivity type having an impurity concentration higher than that of said intermediate region and disposed in a fifth surface portion of said substrate contiguous to said fourth surface portion; a first insulating film disposed on said substrate between said source and resistor regions; a gate electrode disposed on said first insulating film; a drain electrode connected to said drain region; and a source electrode connected to said source region, extending over said gate electrode, said resistor region, and a part of said intermediate region, and electrically insulated by a insulating film therefrom, so that one edge of said source electrode is located above said intermediate region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-10-22 | 1983-04-23 | 1983-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-10-22 | 1987-04-23 | 1987-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-10-22 | 1991-04-23 | 1991-10-23 | $7700.00 | Window Closed / Lapsed |