US3886003A
Expired / Lapsed
US
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Method of making an integrated circuit
Assignee: Fujitsu Ltd
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Filing: 1972-10-03
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Granted: 1975-05-27
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Expires: 1992-10-03
Abstract
Abstract A method of making an integrated circuit including an enhancement mode and a depletion mode transistor is disclosed which employs an N-type semiconductor substrate doped with an Ntype impurity of high vapor pressure such as P, As or Sb and a Ptype impurity of low vapor pressure such as B or Ga at a concentration close to that of the N-type impurity. Further, the substrate of the integrated circuit is subjected to heat in a vacuum with that surface area of the substrate in which a depletion mode transistor will ultimately be formed being exposed and the remaining surface area being masked, thereby to invert the conductivity type of only the exposed surface area to P-type. The P-channel depletion mode transistor is formed in the exposed surface area and the P-channel enhancement mode transistor is formed in the unexposed surface area.
Inventors
- 👤 Mikio Takagi
- 👤 Hajime Kamioka
- 👤 Kazufumi Nakayama
- 👤 Chiaki Terada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:31
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0163; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/151; Y10S438/00; Y10S438/914; Y10S438/919
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
199 words
A method of manufacturing a depletion mode insulated gate field effect transistor and an enhancement mode insulated gate field effect transistor as an integrated semiconductor assembly comprising the steps of: a. providing a semiconductor substrate of one conductivity type doped with an impurity of said one conductivity type having a relatively high vapor pressure and with an impurity of an opposite conductivity type having a relatively low vapor pressure and a concentration approximating that of said impurity of said one conductivity type; b. diffusing an impurity of said opposite conductivity type into selected portions of the surface of said semiconductor substrate to form source and drain regions for both an enhancement mode transistor and a depletion mode transistor; c. masking a selected area of said semiconductor surface so as to expose only that surface area of said semiconductor substrate intermediate the source and drain for said depletion type transistor, and d. heating said semiconductor substrate at a selected temperature in a vacuum to invert the region of said substrate within said intermediate surface area from said one conductivity type to said opposite conductivity type thereby interconnecting the source and drain of said depletion mode transistor with said inverted region.
Claim 2
Independent Claim
199 words
A method of manufacturing a depletion mode insulated gate field effect transistor and an enhancement mode insulated gate field effect transistor as an integrated semiconductor assembly comprising the steps of: a. providing a semiconductor substrate of one conductivity type doped with an impurity of said one conductivity type having a relatively high vapor pressure and with an impurity of an opposite conductivity type having a relatively low vapor pressure and a concentration approximating that of said impurity of said one conductivity type; b. diffusing an impurity of said opposite conductivity type into selected portions of the surface of said semiconductor substrate to form source and drain regions for both an enhancement mode transistor and a depletion mode transistor; c. masking a selected area of said semiconductor surface so as to expose only that surface area of said semiconductor substrate intermediate the source and drain for said depletion type transistor, and d. heating said semiconductor substrate at a selected temperature in a vacuum to invert the region of said substrate within said intermediate surface area from said one conductivity type to said opposite conductivity type thereby interconnecting the source and drain of said depletion mode transistor with said inverted region.
Claim 3
Dependent Claim
51 words
The method of manufacturing an integrated semiconductor assembly as claimed in claim 1, wherein said impurity of said one conductivity type is selected from a group consisting of P, As and Sb, and wherein said impurity of said opposite conductivity type is selected of a group consisting of B and Ga.
Claim 4
Dependent Claim
105 words
The method of manufacturing an integrated semiconductor assembly as claimed in claim 1, wherein said step of forming said source and drain regions includes the steps of forming a first masking layer upon said surface of said semiconductor substrate and selectively removing portions thereof to form windows corresponding to said source and drain regions of said enhancement mode and depletion mode transistors, and introducing as by diffusing through said windows said impurity of said opposite conductivity type into said semiconductor substrate to form said source and drain regions of said enhancement mode and depletion mode transistors, while forming a second masking layer within said windows.
Claim 5
Dependent Claim
51 words
A method of manufacturing an integrated semiconductor assembly as claimed in claim 3, including the steps of removing a portion of the first masking layer corresponding to said gate region of said depletion mode transistor to form a window for the inversion of said substrate region within said intermediate surface area.
Claim 6
Dependent Claim
83 words
A method of manufacturing an integrated semiconductor assembly as claimed in claim 1, wherein said enhancement mode transistor includes an intermediate portion between said source and drain regions and there is included the further steps of forming first and second insulating layers upon said intermediate portions of said enhancement mode and said depletion mode transistors, and thereafter forming electrical contacts directly to said source and drain regions and to said first and second insulating layers of said enhancement mode and depletion mode transistors.
Claim 7
Dependent Claim
39 words
The method of manufacturing an integrated semiconductor assembly as claimed in claim 5, including the steps of forming an electrical connection between said drain region of said enhancement mode transistor and said source region of said depletion mode transistor.
Claim 8
Dependent Claim
40 words
The method of manufacturing an integrated semiconductor assembly as claimed in claim 1, wherein said one conductivity type is an N-type and said opposite conductivity type is a P-type, and P-channel depletion mode and enhancement mode transistors are formed thereby.
Claim 9
Dependent Claim
42 words
THE METHOD OF MANUFACTURING AN INTEGRATED SEMICONDUCTOR ASSEMBLY AS CLAIMED IN CLAIM 1. INCLUDING THE STEPS OF FORMING A GATE INSULATOR ON THE SURFACE AREAS OF SAID SUBSTRATE INTERMEDIATE EACH SOURCE AND DRAIN AND FORMING A GATE ELECTRODE ON SAID GATE INSULATORS.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-26 | 1978-11-25 | 1979-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-26 | 1982-11-25 | 1983-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-26 | 1986-11-25 | 1987-05-27 | $7700.00 | Window Closed / Lapsed |