Integrated circuit structure comprising CMOS transistors having high blocking voltage capability and method of fabrication of said structure

Claim 1

An integrated circuit structure incorporating low-voltage n-channel and p-channel MOS transistors and high-voltage n-channel and p-channel MOS transistors, comprising a semiconductor wafer formed by a substrate covered with a lightly doped n-type epitaxial layer; first lightly doped p - type regions extending from the surface of the semiconductor wafer to part of the depth of the epitaxial layer, these regions being such as to constitute compartments in which are formed the source, the drain and the channel of low-voltage n-channel MOS transistors; heavily doped p + type regions which are of smaller depth than the p - type regions, which extend from the surface of the semiconductor wafer, and which constitute the source and the drain of the p-channel MOS transistors; heavily doped n + type regions which are of smaller depth than the p - type regions, which extend from the surface of the semiconductor wafer, and which constitute the source and the drain of the n-channel MOS transistors; wherein provision is also made for: at least a second p - type region having the same concentration profile as the first regions and extending to the same depth, said second region being adapted to surround an n + type source region and to constitute a channel region of a high-voltage n-channel MOS transistor which further comprises an n + type drain region located outside the second region and in spaced relation thereto so as to permit the existence of a lightly doped n-type epitaxial layer zone not directly controlled by the transistor gate between said drain region and said second region; at least a third p - type region having the same concentration profile as the first and second regions and extending to the same depth, said third region being adapted to surround a p + type drain region of a high-voltage p-channel MOS transistor in which the channel region is constituted by a lightly doped n-type epitaxial layer region adjacent to the third region, the p + type drain region of said transistor being in spaced relation to the channel region so as to form between these latter a zone of the third region which is not directly controlled by the transistor gate, and the source region of said transistor being located outside said third region.