Fabrication process of sub-micrometer channel length MOSFETs

Abstract

Abstract Methods for fabricating a semiconductor integrated circuit having a sub-micrometer gate length field effect transistor devices are described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor from one another. Certain of these semiconductor regions are designated to contain field effect transistor devices. An insulating layer which may be designated to be in part the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern surface. Then a first polycrystalline silicon layer is formed thereover. A masking layer such as silicon dioxide, silicon nitride or the like is then formed upon the first polycrystalline layer. The structure is etched to result in a patterned first polycrystalline silicon layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A controlled sub-micrometer thickness conductive layer is formed on these vertical sidewalls. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness conductive sidewall layer portions of which extend across certain of the device regions. The sidewall conductive layer is utilized as the gate electrode of the field effect transistor devices. Ion implantation is then accomplished to form the desired source/drain element for the field effect devices in the device regions. The conductive layer and resulting gate electrode may be composed of polycrystalline silicon metal silicide or polycide (a combination of layers of polycrystalline silicon and metal silicide).

Inventors

• 👤 Jacob Riseman
• 👤 Paul J. Tsang

Bibliographic Details