US4374700A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing silicide contacts for CMOS devices
Assignee: Texas Instruments Inc
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Filing: 1981-05-29
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Granted: 1983-02-22
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Expires: 2001-05-29
Abstract
Abstract In the manufacture of a CMOS device, oxide is etched away from polysilicon gate-level interconnects, and from source or drain regions of either conductivity type to which the polysilicon gate-level interconnect is desired to be connected. A metal is then deposited, and silicide is formed to connect the gate-level interconnect to the respective source and drain regions. To ensure continuity of the silicide connection, the gate oxide beneath the gate level interconnect is slightly undercut by a wet etching process, additional polysilicon is deposited conformally overall, and the additional polysilicon is anistropically etched so that it is removed from all areas except those within the undercut region beneath the gate-level interconnect thus a continuous surface of silicon, from which a continuous layer of silicide is then grown, exists between the polysilicon gate-level interconnect and the respective source and drain regions. Thus, self-aligned contacts are created, and no unwanted pn junctions are created.
Inventors
- 👤 David B. Scott
- 👤 Roderick D. Davies
- 👤 Yee-Chaung See
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 01:07
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D84/02; H10D84/03; H10D84/038; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10W20/0698; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
154 words
A process for forming contacts between gate-level interconnects, comprising doped polysilicon, and either n or p-type source or drain regions formed in a silicon substrate which is covered by a gate insulator layer, said process comprising the steps of: etching regions of said gate insulator layer where said contacts are to be formed, said etching step also partially undercutting said gate-level interconnects by eroding said gate insulator beneath said gate-level interconnects at the edges thereof where said contacts are to be formed; conformally depositing undoped polysilicon on the resulting composite surface; etching said undoped polysilicon, so as to remove said undoped polysilicon from all areas except those areas where said gate-level interconnects are undercut by said first-mentioned etching step; and siliciding exposed areas of said silicon substrate, said gate-level interconnects, and said conformally deposited undoped polysilicon layer, whereby silicide contacts are formed between said gate-level interconnects and said respective exposed regions of said substrate.
Claim 2
Dependent Claim
154 words
A process for forming contacts between gate-level interconnects, comprising doped polysilicon, and either n or p-type source or drain regions formed in a silicon substrate which is covered by a gate insulator layer, said process comprising the steps of: etching regions of said gate insulator layer where said contacts are to be formed, said etching step also partially undercutting said gate-level interconnects by eroding said gate insulator beneath said gate-level interconnects at the edges thereof where said contacts are to be formed; conformally depositing undoped polysilicon on the resulting composite surface; etching said undoped polysilicon, so as to remove said undoped polysilicon from all areas except those areas where said gate-level interconnects are undercut by said first-mentioned etching step; and siliciding exposed areas of said silicon substrate, said gate-level interconnects, and said conformally deposited undoped polysilicon layer, whereby silicide contacts are formed between said gate-level interconnects and said respective exposed regions of said substrate.
Claim 3
Dependent Claim
13 words
The process of claim 1, wherein said first-mentioned etching step comprises wet etching.
Claim 4
Dependent Claim
13 words
The process of claim 1, wherein said second-mentioned etching step comprises anisotropic etching.
Claim 5
Dependent Claim
42 words
The process of claim 1, 2, or 3 wherein said siliciding step comprises: depositing a metal overall; applying heat, so that said metal reacts with said regions exposed by said first-mentioned etching step; and etching away all unreacted portions of said metal.
Claim 6
Dependent Claim
18 words
The process of claim 4, wherein said metal is selected from the group consisting of platinum and titanium.
Claim 7
Dependent Claim
10 words
The process of claim 5, wherein said metal is titanium.
Claim 8
Dependent Claim
48 words
The process of claim 1, wherein said siliciding step comprises: selectively depositing tungsten above said exposed areas of said silicon substrate, said gate-level interconnect, and said conformally deposited undoped polysilicon layer; and applying heat, so that silicide is formed between said selectedly applied tungsten and said exposed areas.
Claim 9
Dependent Claim
22 words
The process of claim 1, 2, or 3, wherein said first-mentioned etching step also etches the upper surfaces of said gate-level interconnects.
Claim 10
Dependent Claim
174 words
A process for forming contacts between gate-level polysilicon and a silicon substrate, comprising the steps of: providing a silicon substrate; providing an insulator layer on said substrate, said insulator layer comprising gate insulator areas, wherein the thickness of said insulator layer is less than 100 nm; providing polysilicon on selected portions of said insulator layer; etching regions of said gate insulator areas, adjacent to respective portions of said polysilicon, where said contacts are to be formed, said etching step also partially undercutting said portions of said polysilicon where said contacts are to be formed by eroding said insulator layer from beneath the perimeter of said polysilicon; conformally depositing undoped polysilicon overall; anisotropically etching said undoped polysilicon, so as to remove said undoped polysilicon except from said undercuts in said gate insulator layer; and providing metal silicide on exposed areas of said substrate, said gate-level polysilicon, and said undoped polysilicon in said undercuts in said gate insulator areas, whereby silicide contacts are formed between said gate-level polysilicon and said respective exposed regions of said substrate.
Claim 11
Dependent Claim
174 words
A process for forming contacts between gate-level polysilicon and a silicon substrate, comprising the steps of: providing a silicon substrate; providing an insulator layer on said substrate, said insulator layer comprising gate insulator areas, wherein the thickness of said insulator layer is less than 100 nm; providing polysilicon on selected portions of said insulator layer; etching regions of said gate insulator areas, adjacent to respective portions of said polysilicon, where said contacts are to be formed, said etching step also partially undercutting said portions of said polysilicon where said contacts are to be formed by eroding said insulator layer from beneath the perimeter of said polysilicon; conformally depositing undoped polysilicon overall; anisotropically etching said undoped polysilicon, so as to remove said undoped polysilicon except from said undercuts in said gate insulator layer; and providing metal silicide on exposed areas of said substrate, said gate-level polysilicon, and said undoped polysilicon in said undercuts in said gate insulator areas, whereby silicide contacts are formed between said gate-level polysilicon and said respective exposed regions of said substrate.
Claim 12
Dependent Claim
41 words
The process of claim 9, wherein said step of providing silicide comprises: depositing a metal overall; applying heat, so that said metal reacts with said regions exposed by said first-mentioned etching step; and etching away all unreacted portions of said metal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-21 | 1986-08-23 | 1987-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-21 | 1990-08-23 | 1991-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-21 | 1994-08-23 | 1995-02-22 | $7700.00 | Window Closed / Lapsed |