US4033797A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a complementary metal-insulation-semiconductor circuit
Assignee: Raytheon Co
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Filing: 1975-04-23
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Granted: 1977-07-05
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Expires: 1995-04-23
Abstract
Abstract A circuit comprised of interconnected complementary MIS devices is formed in a common semiconducting substrate by forming a plurality of complementary substrate regions in the common substrate, one region for each device whose source and drain regions are to have the same conductivity type as the common substrate. The other devices whose source and drain regions are to have the opposite conductivity type from that of the common substrate are formed directly therein. Interconnections between the devices are provided by a two-layer grid, the bottom layer of which is comprised of polycrystalline silicon conductors which also serve as the gates for the MIS devices. The top layer of the grid is comprised of a second set of conductors which is insulated from the bottom layer but which makes connection thereto and to the source and drain regions as well as to the complementary substrate at selected points. The regions of the substrate between adjacent MIS devices are covered by an oxide layer which extends both below and above the substrate surface and both ion implantation and the use of a doped oxide is disclosed for forming the complementary substrate regions.
Inventors
- 👤 Hans G. Dill
- 👤 Thomas N. Toombs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:04
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; H10P; H10P76/00; H10P76/40
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
193 words
In the process of producing an SIS circuit having at least one N-channel and one P-channel device with interconnected gates in a surface of a semiconductor substrate of a given type of conductivity, the steps of: (a) forming an insulating layer on said surface, said layer having an opening therein for each of said devices; (b) forming a complementary substrate under one of said openings for one of said devices; (c) disposing a gate insulator of electrically insulating material on a portion of said substrate within each of said openings; (d) forming on said layer of insulating material a multi-layered strip comprising an integral strip of electrically conductive polycrystalline silicon doped to have a given type of conductivity to serve as interconnected gates for said devices and a dopant-impervious insulating layer covering said polycrystalline silicon strip; and (e) with said multi-layered strip and said insulating layer as a mask, successively doping selected spaced-apart areas within respective ones of said openings with mutually opposite conductivity type determining impurities to convert them into source and drain regions of opposite conductivity from the substrate immediately surrounding them, without changing the conductivity type of said silicon strip.
Claim 2
Dependent Claim
193 words
In the process of producing an SIS circuit having at least one N-channel and one P-channel device with interconnected gates in a surface of a semiconductor substrate of a given type of conductivity, the steps of: (a) forming an insulating layer on said surface, said layer having an opening therein for each of said devices; (b) forming a complementary substrate under one of said openings for one of said devices; (c) disposing a gate insulator of electrically insulating material on a portion of said substrate within each of said openings; (d) forming on said layer of insulating material a multi-layered strip comprising an integral strip of electrically conductive polycrystalline silicon doped to have a given type of conductivity to serve as interconnected gates for said devices and a dopant-impervious insulating layer covering said polycrystalline silicon strip; and (e) with said multi-layered strip and said insulating layer as a mask, successively doping selected spaced-apart areas within respective ones of said openings with mutually opposite conductivity type determining impurities to convert them into source and drain regions of opposite conductivity from the substrate immediately surrounding them, without changing the conductivity type of said silicon strip.
Claim 3
Dependent Claim
281 words
In the process of producing an SIS circuit, having at least one N channel and one P channel device, with interconnected gates in a surface of a silicon substrate of a given type of conductivity, the steps of: (a) growing a field oxide layer on said silicon surface, said layer having an opening therein for each of said devices; (b) with said oxide layer as a mask, doping said silicon under one of said openings with a conductivity type, so as to form a complementary substrate under said one opening; (c) growing a gate oxide layer within said openings; (d) depositing a doped polycrystalline silicon layer over said oxide layer in said openings; (e) forming a dopant-impervious insulating layer over, and in contact with, said polycrystalline silicon layer; (f) selectively removing portions of said insulating layer to cover thereby that portion of said polycrystalline layer which is to serve as said interconnected gates; (g) with the remaining portion of said insulating layer as a mask selectively etching away portions of said polycrystalline silicon layer to form an integral insulated gate structure extending into both of said openings to serve as the respective insulated gates of both of said devices; and (h) with said insulated gates and said field oxide layer as a mask, and with said insulated gates being protected by the remaining portion of said insulating layer from further doping, successively doping selected spaced-apart areas of silicon substrate within respective ones of said openings with mutually opposite conductivity type determining impurities to convert those areas into source and drain regions of opposite conductivity from the substrate immediately surrounding them, without changing the conductivity type of said integral insulated gate structure.
Claim 4
Dependent Claim
281 words
In the process of producing an SIS circuit, having at least one N channel and one P channel device, with interconnected gates in a surface of a silicon substrate of a given type of conductivity, the steps of: (a) growing a field oxide layer on said silicon surface, said layer having an opening therein for each of said devices; (b) with said oxide layer as a mask, doping said silicon under one of said openings with a conductivity type, so as to form a complementary substrate under said one opening; (c) growing a gate oxide layer within said openings; (d) depositing a doped polycrystalline silicon layer over said oxide layer in said openings; (e) forming a dopant-impervious insulating layer over, and in contact with, said polycrystalline silicon layer; (f) selectively removing portions of said insulating layer to cover thereby that portion of said polycrystalline layer which is to serve as said interconnected gates; (g) with the remaining portion of said insulating layer as a mask selectively etching away portions of said polycrystalline silicon layer to form an integral insulated gate structure extending into both of said openings to serve as the respective insulated gates of both of said devices; and (h) with said insulated gates and said field oxide layer as a mask, and with said insulated gates being protected by the remaining portion of said insulating layer from further doping, successively doping selected spaced-apart areas of silicon substrate within respective ones of said openings with mutually opposite conductivity type determining impurities to convert those areas into source and drain regions of opposite conductivity from the substrate immediately surrounding them, without changing the conductivity type of said integral insulated gate structure.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-04 | 1981-01-03 | 1981-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-04 | 1985-01-03 | 1985-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-04 | 1989-01-03 | 1989-07-05 | $7700.00 | Window Closed / Lapsed |