US3667009A
Expired / Lapsed
US
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Complementary metal oxide semiconductor gate protection diode
Assignee: Motorola Solutions Inc
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Filing: 1970-12-28
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Granted: 1972-05-30
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Expires: 1990-12-28
Abstract
Abstract Gate protection is given to a complementary metal oxide semiconductor (CMOS) devices against excessive input voltage transients. An input diode which has a lower breakdown voltage than the gate oxide is attached to the input terminal to protect the gate oxide. The input protect diode is formed by diffusing an N+ region which overlaps both a P tube and an N substrate. The diffusion concentrations between the various regions determine the breakdown voltage of the protection diode. The overlapping relationship of the N+ diffusion over the P- tub and N substrate creates a structure which prevents parasitic NPN action.
Inventors
- 👤 James M Rugg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:26
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/52; H03F1/523; H03K; H03K17/00; H03K17/08; H03K17/081; H03K17/0812; H03K17/08122; H10; H10D; H10D84/00; H10D84/201; H10D84/204; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/858; H10D89/00; H10D89/60; H10D89/601; H10D89/611; Y; Y10; Y10S; Y10S148/00; Y10S148/049; Y10S148/053; Y10S148/122; Y10S148/136
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
156 words
In combination: a body of semiconductor material of a first conductivity type and having an upper surface; a CMOS device comprising gate, source and drain electrodes in said body; and a voltage sensitive protecting means connectable to said gate electrode for diverting excessive signal voltage from said gate electrode, comprising; a first region extending into said body from said upper surface and being of an opposite conductivity type and forming a first junction with said body, and a second region extending into said body from said upper surface and being of a first conductivity type and being positioned partially overlying said first region and forming a second junction with said first region and an interface with said body; and said second region having a first impurity concentration and said first region having an impurity surface concentration less than said second region for establishing a voltage value above which current flows between said first and second regions.
Claim 2
Dependent Claim
156 words
In combination: a body of semiconductor material of a first conductivity type and having an upper surface; a CMOS device comprising gate, source and drain electrodes in said body; and a voltage sensitive protecting means connectable to said gate electrode for diverting excessive signal voltage from said gate electrode, comprising; a first region extending into said body from said upper surface and being of an opposite conductivity type and forming a first junction with said body, and a second region extending into said body from said upper surface and being of a first conductivity type and being positioned partially overlying said first region and forming a second junction with said first region and an interface with said body; and said second region having a first impurity concentration and said first region having an impurity surface concentration less than said second region for establishing a voltage value above which current flows between said first and second regions.
Claim 3
Dependent Claim
42 words
A voltage sensitive protecting means as recited in claim 1, and further comprising; a third region of higher conductivity than said first region and of said same conductivity type and being positioned within said first region for forming a contact enhancement region.
Claim 4
Dependent Claim
51 words
A voltage sensitive protecting means as recited in claim 2, and further comprising; means including said third region for connecting said gate electrode to said second region upon current flowing from said second region, through said first region and into said body for diverting excessive signal voltage from said gate electrode.
Claim 5
Dependent Claim
62 words
A voltage sensitive protecting means as recited in claim 1, and further comprising: a pAir of spaced third regions of higher conductivity than said first region and being of said same conductivity type and being positioned within said first region for forming contact enhancement regions; and said portion of said semiconductor body positioned between said third regions forming a current limiting resistor.
Claim 6
Dependent Claim
39 words
A voltage sensitive protecting means as recited in claim 4, and further comprising: first means including one of said third regions connected to said gate electrode; and second means including another of said third regions for receiving input signal.
Claim 7
Dependent Claim
302 words
A CMOS device including a voltage sensitive protecting means, comprising: a body of semiconductor material having an upper surface and being of a first conductivity type and relatively high resistivity for forming a first structure of MOS device; a plurality of spaced first regions of opposite conductivity type material extending into said body from said surface and each of said first regions forming a first junction with said body and said first regions being of relatively high resistivity for forming a second structure of MOS device; a plurality of second regions extending into said body from said upper surface and being of a first conductivity type and relatively low resistivity; a first one of said second regions being positioned partially overlying a first one of said first regions and forming a second junction with said first region and an interface with said body; additional ones of said second regions being positioned in a second one of said first regions as a source and drain region of said second MOS device; a plurality of third regions extending into said body from said upper surface and being of an opposite conductivity type and relatively low resistivity; at least a first one of said third regions being positioned within said first one of said first regions for providing a contact enhancement region for said first one of said first regions; additional ones of said third regions being positioned in said body as a source and drain region of said first MOS device; gate electrodes adhering to said upper surface and positioned between said source and drain regions of said first MOS device and said second MOS device; means for establishing a reference potential at said first one of said second regions; and connecting means interconnecting said first of said third regions and said gate electrodes.
Claim 8
Dependent Claim
302 words
A CMOS device including a voltage sensitive protecting means, comprising: a body of semiconductor material having an upper surface and being of a first conductivity type and relatively high resistivity for forming a first structure of MOS device; a plurality of spaced first regions of opposite conductivity type material extending into said body from said surface and each of said first regions forming a first junction with said body and said first regions being of relatively high resistivity for forming a second structure of MOS device; a plurality of second regions extending into said body from said upper surface and being of a first conductivity type and relatively low resistivity; a first one of said second regions being positioned partially overlying a first one of said first regions and forming a second junction with said first region and an interface with said body; additional ones of said second regions being positioned in a second one of said first regions as a source and drain region of said second MOS device; a plurality of third regions extending into said body from said upper surface and being of an opposite conductivity type and relatively low resistivity; at least a first one of said third regions being positioned within said first one of said first regions for providing a contact enhancement region for said first one of said first regions; additional ones of said third regions being positioned in said body as a source and drain region of said first MOS device; gate electrodes adhering to said upper surface and positioned between said source and drain regions of said first MOS device and said second MOS device; means for establishing a reference potential at said first one of said second regions; and connecting means interconnecting said first of said third regions and said gate electrodes.
Claim 9
Dependent Claim
30 words
A CMOS device as recited in claim 6, wherein: said first of said second regions is annular shaped and terminates said junction between said corresponding first region and said body.
Claim 10
Dependent Claim
28 words
A CMOS device as recited in claim 6, wherein: said first MOS device is a P-channel MOS device; and said second MOS device is an N-channel MOS device.
Claim 11
Dependent Claim
64 words
A CMOS device as recited in claim 6, wherein: said third region positioned in said first one of said first regions having a first impurity concentration and said first one of said first regions having an impurity surface concentration less than said last mentioned third region for establishing a voltage value above which current flows between said last mentioned first and third regions respectively.
Claim 12
Dependent Claim
27 words
A CMOS device as recited in claim 6, wherein: said semiconductor body having a resistivity lying within the range of 1 ohm centimeter to 10 ohms centimeter.
Claim 13
Independent Claim
257 words
The method of fabricating a CMOS semiconductor device comprising the steps of: providing a semiconductor body having an upper surface and being of one type, relatively high resistivity material and being suitable for the formation of a first type MOS device; forming a plurality of spaced first regions of opposite conductivity extending into said body from said surface and each of said first regions forming a first junction with said body and said first regions being of relatively high resistivity type material and being suitable for tHe formation of a second type MOS device; establishing a source and drain region of a second type MOS device within a first of said first regions and simultaneously establishing within a second of said first regions a second region comparable to said source and drain regions and said second region being positioned partially overlying said second one of said first regions and forming a second junction with said first region and an interface with said body; establishing a source and drain region of a first type MOS device within said body and simultaneously establishing within said second of said first regions a third region comparable to said source and drain regions of said first type MOS device for operating as a contact enhancement region for said second of said first regions; forming gate electrodes for said first type MOS device and for said second type MOS device; and forming a metallization layer on said upper surface including at least a conductive path between said gate electrodes and said second region.
Claim 14
Independent Claim
257 words
The method of fabricating a CMOS semiconductor device comprising the steps of: providing a semiconductor body having an upper surface and being of one type, relatively high resistivity material and being suitable for the formation of a first type MOS device; forming a plurality of spaced first regions of opposite conductivity extending into said body from said surface and each of said first regions forming a first junction with said body and said first regions being of relatively high resistivity type material and being suitable for tHe formation of a second type MOS device; establishing a source and drain region of a second type MOS device within a first of said first regions and simultaneously establishing within a second of said first regions a second region comparable to said source and drain regions and said second region being positioned partially overlying said second one of said first regions and forming a second junction with said first region and an interface with said body; establishing a source and drain region of a first type MOS device within said body and simultaneously establishing within said second of said first regions a third region comparable to said source and drain regions of said first type MOS device for operating as a contact enhancement region for said second of said first regions; forming gate electrodes for said first type MOS device and for said second type MOS device; and forming a metallization layer on said upper surface including at least a conductive path between said gate electrodes and said second region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-30 | 1975-11-29 | 1976-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-30 | 1979-11-29 | 1980-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-30 | 1983-11-29 | 1984-05-30 | $7700.00 | Window Closed / Lapsed |