Method for forming an insulator between layers of conductive material

Claim 1

A method for forming an insulator between conducting layers comprising: providing a monocrystalline silicon body; forming above the surface of said body conductive material regions having substantially horizontal surfaces and substantially vertical surfaces and having an insulation layer on the said horizontal surfaces; forming a conformal insulator layer on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching said insulator layer to substantially remove said horizontal layer and to provide a narrow dimensioned vertical insulator region on said silicon body while leaving said insulation layer substantially intact; and forming a conductive layer over said vertical insulator.

Claim 2

A method for forming an insulator between conducting layers comprising: providing a monocrystalline silicon body; forming above the surface of said body conductive material regions having substantially horizontal surfaces and substantially vertical surfaces and having an insulation layer on the said horizontal surfaces; forming a conformal insulator layer on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching said insulator layer to substantially remove said horizontal layer and to provide a narrow dimensioned vertical insulator region on said silicon body while leaving said insulation layer substantially intact; and forming a conductive layer over said vertical insulator.

Claim 9

A method for forming bipolar integrated circuit devices having an insulator between conducting layers comprising: providing a silicon body having a pattern of monocrystalline silicon regions isolated from one another; forming a base region in said monocrystalline regions; providing an insulator over the surface of said body having said pattern with openings for the base contacts to said base regions; despositing a layer of polycrystalline silicon over said insulator and said openings therein; forming an insulator coating upon said polycrystalline silicon layer; removing said insulator coating and said polycrystalline silicon layer from where said emitter and collector reach-through are to be formed which results in regions of said polycrystalline layer with said insulator coating thereon having substantially horizontal surfaces and substantially vertical surfaces; forming a conformal insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching said conformal insulating layer to substantially remove said horizontal conformal insulating layer and to provide a narrow dimensioned vertical insulating region on said polycrystalline layer; forming the emitter and collector reach-through regions within said monocrystalline silicon regions; and forming a conductive layer over said vertical insulating region and said insulator coating.

Claim 10

A method for forming bipolar integrated circuit devices having an insulator between conducting layers comprising: providing a silicon body having a pattern of monocrystalline silicon regions isolated from one another; forming a base region in said monocrystalline regions; providing an insulator over the surface of said body having said pattern with openings for the base contacts to said base regions; despositing a layer of polycrystalline silicon over said insulator and said openings therein; forming an insulator coating upon said polycrystalline silicon layer; removing said insulator coating and said polycrystalline silicon layer from where said emitter and collector reach-through are to be formed which results in regions of said polycrystalline layer with said insulator coating thereon having substantially horizontal surfaces and substantially vertical surfaces; forming a conformal insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching said conformal insulating layer to substantially remove said horizontal conformal insulating layer and to provide a narrow dimensioned vertical insulating region on said polycrystalline layer; forming the emitter and collector reach-through regions within said monocrystalline silicon regions; and forming a conductive layer over said vertical insulating region and said insulator coating.

Claim 18

A method for forming a field effect device integrated circuit structure comprising: providing a monocrystalline silicon body; forming a first insulator layer having the desired thickness of the gate insulator on the surface of said body; forming a first polycrystalline silicon layer over said insulator layer; forming a second insulator layer on the surface of said first polycrystalline silicon layer; removing said second insulator layer and said first polycrystalline silicon layer from portions of said first insulator layer to form part of the gate electrode and which results in regions of said polycrystalline layer with said second insulator layer thereon having substantially horizontal surfaces and substantially vertical surfaces; forming a conformal insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching said conformal insulating layer to substantially remove said horizontal conformal insulating layer and to provide a narrow dimensioned vertical insulating region on said polycrystalline layer; forming a second polycrystalline silicon layer over said vertical insulating region, said exposed first insulator layer and said second insulator layer; forming a third insulator layer on said second polycrystalline layer; removing said third insulator layer and said second polycrystalline layer in the desired pattern to connect the said field effect devices in said integrated circuit; removing said second insulator layer and said first polycrystalline layer in the areas where diffused regions are required for said field effect devices and to fully define the said gate electrode pattern; and forming said diffused regions.

Claim 19

A method for forming a field effect device integrated circuit structure comprising: providing a monocrystalline silicon body; forming a first insulator layer having the desired thickness of the gate insulator on the surface of said body; forming a first polycrystalline silicon layer over said insulator layer; forming a second insulator layer on the surface of said first polycrystalline silicon layer; removing said second insulator layer and said first polycrystalline silicon layer from portions of said first insulator layer to form part of the gate electrode and which results in regions of said polycrystalline layer with said second insulator layer thereon having substantially horizontal surfaces and substantially vertical surfaces; forming a conformal insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching said conformal insulating layer to substantially remove said horizontal conformal insulating layer and to provide a narrow dimensioned vertical insulating region on said polycrystalline layer; forming a second polycrystalline silicon layer over said vertical insulating region, said exposed first insulator layer and said second insulator layer; forming a third insulator layer on said second polycrystalline layer; removing said third insulator layer and said second polycrystalline layer in the desired pattern to connect the said field effect devices in said integrated circuit; removing said second insulator layer and said first polycrystalline layer in the areas where diffused regions are required for said field effect devices and to fully define the said gate electrode pattern; and forming said diffused regions.