Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
290 words
A process for forming lightly doped drains (LDDs) on both NMOS and PMOS devices together on a CMOS integrated circuit using only one mask level, comprising the following steps in the following sequence: forming gates for NMOS and PMOS devices on an integrated circuit substrate; forming disposable, cleanly removable sidewall spacers along the gate edges; protecting gates of a first conductivity type by covering them with a disposable barrier material; implanting heavily doped source/drain regions along sidewall spacer edges of gates of a second conductivity type, while gates of the first conductivity type are protected by the disposable barrier material; removing the disposable sidewall spacer from along the edges of the gates of the second conductivity type; implanting LDDs along the gate edges of the second conductivity while the gates of the first conductivity type are protected by a disposable barrier material; removing the disposable barrier material; driving in the source/drain regions and LDDs along the gate edges of the second conductivity type in a first thermal drive-in cycle in an oxidizing ambient to grow silicon dioxide over the surface of the substrate wherein the oxide over the source/drain regions and LDDs by the gates of the second conductivity type is thicker than the oxide over future source/drain regions by the gates of the first conductivity type; reforming disposable, cleanly removable sidewall spacers along the gate edges; implanting heavily doped source/drain regions along the edges of the sidewall spacers of gates of the first conductivity type; removing all disposable sidewall spacers from along the gate edges; implanting LDDs along the gate edges of the first conductivity type; and driving in the source/drain regions and LDDs along the gate edges of the first conductivity type in a second thermal drive-in cycle.
Claim 2
Dependent Claim
290 words
A process for forming lightly doped drains (LDDs) on both NMOS and PMOS devices together on a CMOS integrated circuit using only one mask level, comprising the following steps in the following sequence: forming gates for NMOS and PMOS devices on an integrated circuit substrate; forming disposable, cleanly removable sidewall spacers along the gate edges; protecting gates of a first conductivity type by covering them with a disposable barrier material; implanting heavily doped source/drain regions along sidewall spacer edges of gates of a second conductivity type, while gates of the first conductivity type are protected by the disposable barrier material; removing the disposable sidewall spacer from along the edges of the gates of the second conductivity type; implanting LDDs along the gate edges of the second conductivity while the gates of the first conductivity type are protected by a disposable barrier material; removing the disposable barrier material; driving in the source/drain regions and LDDs along the gate edges of the second conductivity type in a first thermal drive-in cycle in an oxidizing ambient to grow silicon dioxide over the surface of the substrate wherein the oxide over the source/drain regions and LDDs by the gates of the second conductivity type is thicker than the oxide over future source/drain regions by the gates of the first conductivity type; reforming disposable, cleanly removable sidewall spacers along the gate edges; implanting heavily doped source/drain regions along the edges of the sidewall spacers of gates of the first conductivity type; removing all disposable sidewall spacers from along the gate edges; implanting LDDs along the gate edges of the first conductivity type; and driving in the source/drain regions and LDDs along the gate edges of the first conductivity type in a second thermal drive-in cycle.
Claim 3
Dependent Claim
19 words
The process of claim 8 in which only one mask level is employed in the formation of the LDDs.
Claim 4
Dependent Claim
44 words
The process of claim 8 in which source/drain regions and LDDs are formed around the gates of the first conductivity type previously protected by the disposable barrier material, after the drive-in step for the source/drain regions around the gates of the second conductivity type.
Claim 5
Dependent Claim
67 words
The process of claim 3 in which, after the drive-in step for the source/drain regions around the gates of the second conductivity type, a dielectric is grown in a selectively thick pattern to protect the LDDs and source/- drain regions along the gates of the second conductivity type previously formed, during formation of LDDs and source/drain regions along the edges of gates of the first conductivity type.
Claim 6
Dependent Claim
31 words
The process of claim 3 in which, after the drive-in step for the source/drain regions around the gates of the second conductivity type, permanent spacers are formed along all gate edges.
Claim 7
Dependent Claim
21 words
The process of claim 1 in which a high energy p - implant is employed to form p - pocket regions.
Claim 8
Dependent Claim
274 words
A process for forming lightly doped drains (LDDs) on both NMOS and PMOS devices together on a CMOS integrated circuit using only one mask level comprising the following steps in the following sequence: forming gates for NMOS and PMOS devices on p areas and n areas respectively; forming disposable, cleanly removable sidewall spacers along the gate edges; deposting a resist mask over gates of a first conductivity type; implanting heavily doped source/drain regions along the edges of the sidewall spacers of gates of a second conductivity type; removing the disposable sidewall spacers from along the gate edges of the second conductivity type; implanting LDDs along the gate edges of the second conductivity type; stripping the resist mask from the gates of the first conductivity type; removing the remaining disposable sidewall spacers; driving in the source/drain regions and LDDs along the gate edges of the second conductivity type in a first thermal drive-in cycle in an oxidizing ambient to grow silicon dioxide over the surface of the substrate wherein the oxide over the source/drain regions and LDDs by the gates of the second conductivity type is thicker than the oxide over future source/drain regions by the gates of the first conductivity type; reforming disposable, cleanly removable sidewall spacers along the gate edges; implanting heavily doped source/drain regions along the edges of the sidewall spacers of gates of the first conductivity type; removing all disposable sidewall spacers from along the gate edges; implanting LDDs along the gate edges of the first conductivity type; and driving in the source/drain regions and LDDs along the gate edges of the first conductivity type in a second thermal drive-in cycle.
Claim 9
Dependent Claim
274 words
A process for forming lightly doped drains (LDDs) on both NMOS and PMOS devices together on a CMOS integrated circuit using only one mask level comprising the following steps in the following sequence: forming gates for NMOS and PMOS devices on p areas and n areas respectively; forming disposable, cleanly removable sidewall spacers along the gate edges; deposting a resist mask over gates of a first conductivity type; implanting heavily doped source/drain regions along the edges of the sidewall spacers of gates of a second conductivity type; removing the disposable sidewall spacers from along the gate edges of the second conductivity type; implanting LDDs along the gate edges of the second conductivity type; stripping the resist mask from the gates of the first conductivity type; removing the remaining disposable sidewall spacers; driving in the source/drain regions and LDDs along the gate edges of the second conductivity type in a first thermal drive-in cycle in an oxidizing ambient to grow silicon dioxide over the surface of the substrate wherein the oxide over the source/drain regions and LDDs by the gates of the second conductivity type is thicker than the oxide over future source/drain regions by the gates of the first conductivity type; reforming disposable, cleanly removable sidewall spacers along the gate edges; implanting heavily doped source/drain regions along the edges of the sidewall spacers of gates of the first conductivity type; removing all disposable sidewall spacers from along the gate edges; implanting LDDs along the gate edges of the first conductivity type; and driving in the source/drain regions and LDDs along the gate edges of the first conductivity type in a second thermal drive-in cycle.
Claim 10
Dependent Claim
41 words
The process of claim 7 in which after the drive-in step for the source/drain regions of the second conductivity type, a high energy blanket p - implant is employed before any subsequent sidewall formation to form eventual p - pocket regions.
Claim 11
Dependent Claim
272 words
A process for forming lightly doped drains (LDDs) on both NMOS and PMOS devices together on a CMOS integrated circuit using only one mask level comprising the following steps in the following sequence: first forming gates for NMOS and PMOS devices on p areas and n areas respectively; next forming disposable, cleanly removable sidewall spacers along the gate edges; then depositing a resist mask over gates of a first conductivity type; next implanting heavily doped source/drain regions along the edges of the sidewall spacers of gates of a second conductivity type; subsequently removing the disposable sidewall spacers from along the gate edges of the second conductivity type; next implanting LDDs along the gate edges of the second conductivity type; then stripping the resist mask from the gates of the first conductivity type; next removing substantially all of the remaining disposable sidewall spacers; subsequently driving in the source/drain regions and LDDs along the gate edges of the second conductivity type in a first thermal drive-in cycle in an oxidizing ambient to grow silicon dioxide over the surface of the substrate wherein the oxide over the source/drain regions and LDDs by the gates of the second conductivity type is thicker than the oxide over the future source/drain regions by the gates of the first conductivity type; next implanting LDDs along the gate edges of the first conductivity type; then forming permanent spacers along the gate edges; next implanting heavily doped source/drain regions along the gate edges of the first conductivity type; and subsequently driving the source/drain regions and LDDs along the gate edges of the first conductivity type in a second thermal drive-in cycle.
Claim 12
Dependent Claim
272 words
A process for forming lightly doped drains (LDDs) on both NMOS and PMOS devices together on a CMOS integrated circuit using only one mask level comprising the following steps in the following sequence: first forming gates for NMOS and PMOS devices on p areas and n areas respectively; next forming disposable, cleanly removable sidewall spacers along the gate edges; then depositing a resist mask over gates of a first conductivity type; next implanting heavily doped source/drain regions along the edges of the sidewall spacers of gates of a second conductivity type; subsequently removing the disposable sidewall spacers from along the gate edges of the second conductivity type; next implanting LDDs along the gate edges of the second conductivity type; then stripping the resist mask from the gates of the first conductivity type; next removing substantially all of the remaining disposable sidewall spacers; subsequently driving in the source/drain regions and LDDs along the gate edges of the second conductivity type in a first thermal drive-in cycle in an oxidizing ambient to grow silicon dioxide over the surface of the substrate wherein the oxide over the source/drain regions and LDDs by the gates of the second conductivity type is thicker than the oxide over the future source/drain regions by the gates of the first conductivity type; next implanting LDDs along the gate edges of the first conductivity type; then forming permanent spacers along the gate edges; next implanting heavily doped source/drain regions along the gate edges of the first conductivity type; and subsequently driving the source/drain regions and LDDs along the gate edges of the first conductivity type in a second thermal drive-in cycle.
Claim 13
Dependent Claim
41 words
The process of claim 9 in which after the drive-in step for the source/drain regions of the second conductivity type, a high energy blanket p - implant is employed before any subsequent sidewall formation to form eventual p - pocket regions.