← Back to Patent Explorer
US4488351A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for manufacturing semiconductor device

Assignee: Toshiba Corp
•
Filing: 1984-01-25
•
Granted: 1984-12-18
•
Expires: 2004-01-25
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method for manufacturing a semiconductor device, capable of forming, with good controllability, impurity regions of a low impurity concentration, includes the steps of: forming a gate electrode on a surface of a semiconductor substrate through a gate oxide film; forming a first film on the surfaces of the gate electrode and the semiconductor substrate; forming a non-single-crystalline silicon film to cover the entire surface; forming a second film to cover the entire surface; performing anisotropic etching of the second film to form residual second films on the side walls of that step portion non-single-crystalline silicon film which is formed corresponding to a shape of the gate electrode; performing etching of the non-single-crystalline silicon film by using the residual second films as masks to form residual non-single-crystalline silicon films on the side walls of the gate electrode through the first film; ion-implanting an impurity having a conductivity type opposite to that of the semiconductor substrate by using as masks the gate electrode and the residual non-single-crystalline silicon films; removing the residual non-single-crystalline silicon films; and annealing a resultant structure to activate the impurity so as to form source and drain regions each of which comprises an impurity region of a high impurity concentration and an impurity region of a low impurity concentration which is adjacent to the impurity region of the high impurity concentration and which is located under a structure area corresponding to one of the removed non-single-crystalline silicon films.

Inventors

  • 👤 Hiroshi Momose

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 09:29
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/015; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 234 words
A method for manufacturing a semiconductor device, comprising the steps of: forming a gate electrode on a surface of a gate oxide film on a semiconductor substrate; forming a first film on surfaces of said gate electrode and said semiconductor substrate; forming a non-single-crystalline silicon film to cover an entire surface; forming a second film to cover an entire surface; performing anisotropic or reactive ion etching of said second film to form residual second films on side walls of that step portion non-single-crystalline silicon film which is formed corresponding to a shape of said gate electrode; performing anisotropic or reactive ion etching of said non-single-crystalline silicon film using said residual second films as masks to form residual non-single-crystalline silicon films on said side walls of said gate electrode through said first film; ion-implanting an impurity having a conductivity type opposite to that of said semiconductor substrate using as masks said gate electrode and said residual non-single-crystalline silicon films; removing said residual non-single-crystalline silicon films; and annealing a resultant structure to activate the impurity so as to form source and drain regions each of which comprises an impurity region of a high impurity concentration and an impurity region of a low impurity concentration which is adjacent to said impurity region of high impurity concentration and which is located under a structure area corresponding to one of said residual non-single-crystalline silicon films which have been removed.
Claim 2
Independent Claim 234 words
A method for manufacturing a semiconductor device, comprising the steps of: forming a gate electrode on a surface of a gate oxide film on a semiconductor substrate; forming a first film on surfaces of said gate electrode and said semiconductor substrate; forming a non-single-crystalline silicon film to cover an entire surface; forming a second film to cover an entire surface; performing anisotropic or reactive ion etching of said second film to form residual second films on side walls of that step portion non-single-crystalline silicon film which is formed corresponding to a shape of said gate electrode; performing anisotropic or reactive ion etching of said non-single-crystalline silicon film using said residual second films as masks to form residual non-single-crystalline silicon films on said side walls of said gate electrode through said first film; ion-implanting an impurity having a conductivity type opposite to that of said semiconductor substrate using as masks said gate electrode and said residual non-single-crystalline silicon films; removing said residual non-single-crystalline silicon films; and annealing a resultant structure to activate the impurity so as to form source and drain regions each of which comprises an impurity region of a high impurity concentration and an impurity region of a low impurity concentration which is adjacent to said impurity region of high impurity concentration and which is located under a structure area corresponding to one of said residual non-single-crystalline silicon films which have been removed.
Claim 3
Dependent Claim 66 words
A method according to claim 1, further comprising the step of ion-implanting the impurity having the conductivity type opposite to that of said semiconductor substrate at a dose lower than that of ion implantation using said residual non-single-crystalline silicon films as the masks, using said gate electrode as the mask, before said non-single-crystalline silicon film is formed or after said residual non-single-crystalline silicon films are removed.
Claim 4
Dependent Claim 85 words
A method according to claim 2, further comprising the step of ion-implanting the impurity having the same conductivity type as that of said semiconductor substrate at a depth greater than that of ion implantation using the impurity having the conductivity type opposite to that of said semiconductor substrate, using one of said gate electrode and said residual non-single-crystalline silicon films as a mask/masks before said non-single-crystalline silicon film is formed or after said non-single-crystalline silicon film is etched using said residual second films as masks.
Claim 5
Dependent Claim 47 words
A method according to claim 1, wherein ion implantation of the impurity having the conductivity type opposite to that of said semiconductor substrate comprises ion implantation steps of two impurities, one of which is easy to diffuse and the other one of which is difficult to diffuse.
Claim 6
Dependent Claim 85 words
A method according to claim 4, further comprising the step of ion-implanting the impurity having the same conductivity type as that of said semiconductor substrate at a depth greater than that of ion implantation using the impurity having the conductivity type opposite to that of said semiconductor substrate, using one of said gate electrode and said residual non-single-crystalline silicon films as a mask/masks before said non-single-crystalline silicon film is formed or after said non-single-crystalline silicon film is etched using said residual second films as masks.
Claim 7
Dependent Claim 23 words
A method according to claim 1, wherein said non-single-crystalline silicon film comprises one of a polycrystalline silicon film and an amorphous silicon film.
Claim 8
Dependent Claim 22 words
A method according to claim 1, wherein said first film comprises one of a silicon oxide film and a silicon nitride film.
Claim 9
Dependent Claim 34 words
A method according to claim 1, wherein said second film comprises a film selected from the group consisting of a silicon oxide film, a silicon nitride film, an aluminum film and a molybdenum film.
Claim 10
Dependent Claim 42 words
A method according to claim 1, wherein said non-single-crystalline silicon film has a thickness of 0.1 to 1 μm, said first film has a thickness of 100 to 500 Å, and said second film has a thickness of 100 to 1,000 Å.

References Cited (Backward Citations)

US4292156A Cited
US4209350A Cited
US4376336A Cited
US4356623A Cited
US4356623B1 Cited
US4337132A Cited
US4432132A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-12-18 1988-06-18 1988-12-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-12-18 1992-06-18 1992-12-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-12-18 1996-06-18 1996-12-18 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag