Method of making CMOS circuits by twin tub process and multiple implantations

Claim 1

A method for manufacturing VLSI complementary MOS field effect transistor circuits wherein n-doped tubs are generated in a silicon substrate for acceptance of p-channel transistors of the circuit, corresponding dopant atoms being introduced into said tubs by means of multiple ion implantations for setting various transistor threshold voltages, comprising the steps of: (a) applying a first double layer comprising silicon oxide and silicon nitride to a p-doped silicon substrate; (b) manufacturing the n-doped tubs by means of an ion implantation after completion of masking of remaining regions with a photoresist mask and after removal of the silicon nitride layer at the n-tub region, the implantation utilizing one of the elements selected from the group consisting of phosphorous, arsenic, and antimony; (c) stripping the photoresist mask; (d) performing a local oxidation process for generating a masking oxide for a following deep boron implantation outside of the n-tub region and first in-diffusion step of the phosphorous, arsenic or antimony ions; (e) stripping the silicon nitride structures followed by a selective drive-in of the n-tub; (f) executing a first boron ion implantation; (g) providing a surface-wide stripping of the oxide mask; (h) applying a second double layer comprising silicon oxide and silicon nitride to the substrate surface and structuring the silicon nitride layer covered with a photoresist mask such that n-channel and p-channel active transistor regions to be formed remain covered by the silicon nitride layer; (i) stripping the photoresist mask; (j) applying a further photoresist layer over the n-tub regions; (k) executing a second boron ion implantation for generating n-channel field-implanted regions; (l) stripping the photoresist structures; (m) generating the field oxide regions by means of local oxidation by use of the silicon nitride layer as mask; (n) removing the silicon nitride layer and the oxide layer lying therebelow and executing an oxidation process for manufacturing the gate oxide; (o) executing a third, surface-wide boron ion implantation for doping the n-channel and the p-channel whereby the implantation dosage is selected in conformity with the other implantations such that as symmetrical as possible a threshold voltage |U T | is achieved for the n-channel and the p-channel transistors; (p) depositing and structuring gate regions on the gate oxide at the transistor regions; (q) to create source/drain regions for the n-channel transistors, executing an ion implantation in the n-channel transistor region after masking the n-tub regions with photoresist, said ion implantation utilizing one of the elements selected from the group consisting of arsenic and antimony; (r) executing an oxidation process after stripping the photoresist masking such that an oxide layer thus created in the n-tub region does not mask a subsequent source/drain implantation of the p-channel transistors but such that it can have a masking effect in a region of edges of the polysilicon gate; (s) executing a photoresist technique for masking the n-channel transistor region; (t) executing a fourth boron ion implantation for generating the source/drain regions of the p-channel transistors; (u) removing the photoresist masking; and (v) depositing an insulating layer, etching a contact hole therein, and forming a metal interconnect level thereafter.

Claim 2

A method for manufacturing VLSI complementary MOS field effect transistor circuits wherein n-doped tubs are generated in a silicon substrate for acceptance of p-channel transistors of the circuit, corresponding dopant atoms being introduced into said tubs by means of multiple ion implantations for setting various transistor threshold voltages, comprising the steps of: (a) applying a first double layer comprising silicon oxide and silicon nitride to a p-doped silicon substrate; (b) manufacturing the n-doped tubs by means of an ion implantation after completion of masking of remaining regions with a photoresist mask and after removal of the silicon nitride layer at the n-tub region, the implantation utilizing one of the elements selected from the group consisting of phosphorous, arsenic, and antimony; (c) stripping the photoresist mask; (d) performing a local oxidation process for generating a masking oxide for a following deep boron implantation outside of the n-tub region and first in-diffusion step of the phosphorous, arsenic or antimony ions; (e) stripping the silicon nitride structures followed by a selective drive-in of the n-tub; (f) executing a first boron ion implantation; (g) providing a surface-wide stripping of the oxide mask; (h) applying a second double layer comprising silicon oxide and silicon nitride to the substrate surface and structuring the silicon nitride layer covered with a photoresist mask such that n-channel and p-channel active transistor regions to be formed remain covered by the silicon nitride layer; (i) stripping the photoresist mask; (j) applying a further photoresist layer over the n-tub regions; (k) executing a second boron ion implantation for generating n-channel field-implanted regions; (l) stripping the photoresist structures; (m) generating the field oxide regions by means of local oxidation by use of the silicon nitride layer as mask; (n) removing the silicon nitride layer and the oxide layer lying therebelow and executing an oxidation process for manufacturing the gate oxide; (o) executing a third, surface-wide boron ion implantation for doping the n-channel and the p-channel whereby the implantation dosage is selected in conformity with the other implantations such that as symmetrical as possible a threshold voltage |U T | is achieved for the n-channel and the p-channel transistors; (p) depositing and structuring gate regions on the gate oxide at the transistor regions; (q) to create source/drain regions for the n-channel transistors, executing an ion implantation in the n-channel transistor region after masking the n-tub regions with photoresist, said ion implantation utilizing one of the elements selected from the group consisting of arsenic and antimony; (r) executing an oxidation process after stripping the photoresist masking such that an oxide layer thus created in the n-tub region does not mask a subsequent source/drain implantation of the p-channel transistors but such that it can have a masking effect in a region of edges of the polysilicon gate; (s) executing a photoresist technique for masking the n-channel transistor region; (t) executing a fourth boron ion implantation for generating the source/drain regions of the p-channel transistors; (u) removing the photoresist masking; and (v) depositing an insulating layer, etching a contact hole therein, and forming a metal interconnect level thereafter.

Claim 14

A method for manufacturing VLSI complementary MOS field effect transistor circuits wherein n-doped tubs are generated in a silicon substrate for acceptance of transistors of the circuit, corresponding dopant atoms being introduced into said tubs by means of multiple ion implantations for setting various transistor threshold voltages, comprising the steps of: (a) applying a first double layer comprising silicon oxide and silicon nitride to a p-doped silicon substrate; (b) manufacturing the n-doped tubs by means of an ion implantation after completion of masking of remaining regions with a photoresist mask and after removal of the silicon nitride layer at the n-tub region, the implantation utilizing one of the elements selected from the group consisting of phosphorous, arsenic, and antimony; (c) stripping the photoresist mask; (d) performing a local oxidation process for generating a masking oxide for a following deep borom implantation outside of the n-tub region and a first in-diffusion step of the phosphorous, arsenic or antimony ions; (e) stripping the silicon nitride structures followed by a selective drive-in of the n-tub; (f) executing a first boron ion implantation; (g) providing a surface-wide stripping the oxide mask; (h) applying a second double layer comprising silicon oxide and silicon nitride to the substrate surface, and structuring the silicon nitride layer covered with a photoresist mask such that n-channel and p-channel active transistor regions to be formed remain covered by the silicon nitride layer; (i) stripping the photoresist mask; (j) applying a further photoresist layer over the n-tub regions; (k) executing a second boron ion implantation for generating n-channel field-implanted regions; (l) stripping the photoresist structures; (m) generating the field oxide regions by means of local oxidation by use of the silicon nitride layer as mask; (n) removing the silicon nitride layer and the oxide layer lying therebelow and executing an oxidation process for manufacturing the gate oxide; (o) executing a third, surface-wide boron ion implantation for doping the n-channel and the p-channel whereby the implantation dosage is selected in conformity with the other implantations such that as symmetrical as possible a threshold voltage |U T | is achieved for the n-channel and the p-channel transistors; (p) depositing and structuring gate regions on the gate oxide at the transistor regions; (q) executing an oxidation process after stripping of the photoresist masking such that an oxide layer thus created in the n-tub region does not mask a subsequent source/drain implantation of the p-channel transistors but such that it can have a masking effect in a region of edges of the polysilicon gate; (r) to create source/drain regions for the n-channel transistors, executing a phosphorous ion implantation in the n-channel transistor region after masking the n-tub regions with photoresist; (s) executing a photoresist technique for masking the n-channel transistor region; (t) executing a fourth boron ion implantation for generating the source/drain regions of the p-channel transistors; (u) removing the photoresist masking; and (v) depositing an insulating layer, etching a contact hole therein, and forming a metal interconnect level thereafter.

Claim 15

A method for manufacturing VLSI complementary MOS field effect transistor circuits wherein n-doped tubs are generated in a silicon substrate for acceptance of transistors of the circuit, corresponding dopant atoms being introduced into said tubs by means of multiple ion implantations for setting various transistor threshold voltages, comprising the steps of: (a) applying a first double layer comprising silicon oxide and silicon nitride to a p-doped silicon substrate; (b) manufacturing the n-doped tubs by means of an ion implantation after completion of masking of remaining regions with a photoresist mask and after removal of the silicon nitride layer at the n-tub region, the implantation utilizing one of the elements selected from the group consisting of phosphorous, arsenic, and antimony; (c) stripping the photoresist mask; (d) performing a local oxidation process for generating a masking oxide for a following deep borom implantation outside of the n-tub region and a first in-diffusion step of the phosphorous, arsenic or antimony ions; (e) stripping the silicon nitride structures followed by a selective drive-in of the n-tub; (f) executing a first boron ion implantation; (g) providing a surface-wide stripping the oxide mask; (h) applying a second double layer comprising silicon oxide and silicon nitride to the substrate surface, and structuring the silicon nitride layer covered with a photoresist mask such that n-channel and p-channel active transistor regions to be formed remain covered by the silicon nitride layer; (i) stripping the photoresist mask; (j) applying a further photoresist layer over the n-tub regions; (k) executing a second boron ion implantation for generating n-channel field-implanted regions; (l) stripping the photoresist structures; (m) generating the field oxide regions by means of local oxidation by use of the silicon nitride layer as mask; (n) removing the silicon nitride layer and the oxide layer lying therebelow and executing an oxidation process for manufacturing the gate oxide; (o) executing a third, surface-wide boron ion implantation for doping the n-channel and the p-channel whereby the implantation dosage is selected in conformity with the other implantations such that as symmetrical as possible a threshold voltage |U T | is achieved for the n-channel and the p-channel transistors; (p) depositing and structuring gate regions on the gate oxide at the transistor regions; (q) executing an oxidation process after stripping of the photoresist masking such that an oxide layer thus created in the n-tub region does not mask a subsequent source/drain implantation of the p-channel transistors but such that it can have a masking effect in a region of edges of the polysilicon gate; (r) to create source/drain regions for the n-channel transistors, executing a phosphorous ion implantation in the n-channel transistor region after masking the n-tub regions with photoresist; (s) executing a photoresist technique for masking the n-channel transistor region; (t) executing a fourth boron ion implantation for generating the source/drain regions of the p-channel transistors; (u) removing the photoresist masking; and (v) depositing an insulating layer, etching a contact hole therein, and forming a metal interconnect level thereafter.

Claim 16

A method for manufacturing VLSI complementary MOS field effect transistor circuits comprising the steps of: (a) applying a first double layer comprising silicon oxide and silicon nitride to a p-doped silicon substrate; (b) manufacturing the n-doped tubs by means of an ion implantation after completion of masking of remaining regions with a photoresist mask and after removal of the silicon nitride layer at the n-tub region, the implantation utilizing one of the elements selected from the group consisting of phosphorous, arsenic, and antimony; (c) stripping the photoresist mask; (d) performing a local oxidation process for generating a masking oxide for a following deep boron implantation outside of the n-tub region and a first in-diffusion step of the phosphorous, arsenic or antimony ions; (e) stripping the silicon nitride structures following the selective drive-in of the n-tub; (f) executing a first boron ion implantation; (g) providing surface-wide stripping of the oxide mask; (h) applying a second double layer comprising silicon oxide and silicon nitride to the substrate surface and structuring the silicon nitride layer covered with a photoresist mask such that n-channel and p-channel active transistor regions to be formed remain covered by the silicon nitride layer; (i) stripping the photoresist mask; (j) applying a further photoresist layer over the n-tub regions; (k) executing a second boron ion implantation for generating n-channel field-implanted regions; (l) stripping the photoresist structures; (m) generating the field oxide regions by means of local oxidation by use of the silicon nitride layer as mask; (n) removing the silicon nitride layer and the oxide layer lying therebelow and executing an oxidation process for manufacturing the gate oxide; (o) executing a third, surface-wide boron ion implantation for doping the n-channel and the p-channel transistors; (p) depositing and structuring gate regions on the gate oxide at the transistor regions; (q) to create source/drain regions for the n-channel transistors, executing an ion implantation in the n-channel transistor region after masking the n-tub regions with photoresist, said ion implantation utilizing one of the elements selected from the group consisting of arsenic and antimony; (r) executing an oxidation process after stripping the photoresist masking such that an oxide layer thus created in the n-tub region does not mask a subsequent source/drain implantation of the p-channel transistors but such that it can have a masking effect in a region of edges of the polysilicon gate; (s) executing a photoresist technique for masking the n-channel transistor region; (t) executing a fourth boron ion implantation for generating the source/drain regions of the p-channel transistors; (u) removing the photoresist masking; and (v) depositing an insulating layer, etching a contact hole therein, and forming a metal interconnect level thereafter.

Claim 17

A method for manufacturing VLSI complementary MOS field effect transistor circuits comprising the steps of: (a) applying a first double layer comprising silicon oxide and silicon nitride to a p-doped silicon substrate; (b) manufacturing the n-doped tubs by means of an ion implantation after completion of masking of remaining regions with a photoresist mask and after removal of the silicon nitride layer at the n-tub region, the implantation utilizing one of the elements selected from the group consisting of phosphorous, arsenic, and antimony; (c) stripping the photoresist mask; (d) performing a local oxidation process for generating a masking oxide for a following deep boron implantation outside of the n-tub region and a first in-diffusion step of the phosphorous, arsenic or antimony ions; (e) stripping the silicon nitride structures following the selective drive-in of the n-tub; (f) executing a first boron ion implantation; (g) providing surface-wide stripping of the oxide mask; (h) applying a second double layer comprising silicon oxide and silicon nitride to the substrate surface and structuring the silicon nitride layer covered with a photoresist mask such that n-channel and p-channel active transistor regions to be formed remain covered by the silicon nitride layer; (i) stripping the photoresist mask; (j) applying a further photoresist layer over the n-tub regions; (k) executing a second boron ion implantation for generating n-channel field-implanted regions; (l) stripping the photoresist structures; (m) generating the field oxide regions by means of local oxidation by use of the silicon nitride layer as mask; (n) removing the silicon nitride layer and the oxide layer lying therebelow and executing an oxidation process for manufacturing the gate oxide; (o) executing a third, surface-wide boron ion implantation for doping the n-channel and the p-channel transistors; (p) depositing and structuring gate regions on the gate oxide at the transistor regions; (q) to create source/drain regions for the n-channel transistors, executing an ion implantation in the n-channel transistor region after masking the n-tub regions with photoresist, said ion implantation utilizing one of the elements selected from the group consisting of arsenic and antimony; (r) executing an oxidation process after stripping the photoresist masking such that an oxide layer thus created in the n-tub region does not mask a subsequent source/drain implantation of the p-channel transistors but such that it can have a masking effect in a region of edges of the polysilicon gate; (s) executing a photoresist technique for masking the n-channel transistor region; (t) executing a fourth boron ion implantation for generating the source/drain regions of the p-channel transistors; (u) removing the photoresist masking; and (v) depositing an insulating layer, etching a contact hole therein, and forming a metal interconnect level thereafter.