Method for manufacturing VLSI complementary MOS field effect transistor circuits in silicon gate technology

Claim 1

In a method for producing VLSI complementary MOS field effect transistor circuits in silicon gate technology, particularly with switched capacitors of double polysilicon structures contained in such circuits, in which the process steps for defining the tub for acceptance of the n- or, respectively, the p-channel transistors, for forming the field and channel implantations for active MOS regions of said circuits, as well as for the forming of field oxide regions and the gate oxide and the deposition and etching of the polysilicon-1 level for formation of gate regions and capacitance structures occur in a known manner, wherein the improvement comprises a sequence of the following steps: (a) thermally oxidizing the entire surface to such a degree that an oxide layer thickness, d 4 , over the polysilicon structures (5a, 5b) corresponds to a desired thickness of an insulating layer for the capacitance structures, whereby at the same time, the oxide layer thickness, d 3 , over the source/drain regions (11) is determined, such regions not being masked in an ion implantation (10) occuring later for forming the source/drain regions of the p-channel transistors (11); (b) depositing a surface-wide silicon nitride layer (7) masking the source/drain regions (11) of the p-channel transistors in a layer thickness matched to the implantation energy level utilized in a subsequent source/drain implantation (8); (c) etching the silicon nitride layer (7a, 7b) in such a manner that regions of the p-channel transistors (11) as well as the polysilicon structures (5b) provided for capacitances remained covered by the etched silicon nitride layer; (d) implanting ions non-selectively for forming the source/drain regions (9) of the n-channel transistors; (e) thermally oxidizing the entire surface to such a degree that the oxide layer thickness, d 6 , over the surface/drain regions of the n-channel transistors is sufficient as a masking layer for a subsequent implantation (10) utilized for generating the source/drain regions (11) of the p-channel transistors; (f) removing the nitride layer structures (7a, 7b); (g) implanting ions non-selectively for forming the source/drain regions (11) of the p-channel transistors; (h) depositing and etching a polysilicon-2 level (12) for the capacitance structures; and (i) forming an insulating layer (14), contact hole regions and metal interconnect level (15) in a known manner.