US4280272A
Expired / Lapsed
US
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Method for preparing complementary semiconductor device
Assignee: Toshiba Corp
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Filing: 1979-10-17
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Granted: 1981-07-28
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Expires: 1999-10-17
Abstract
Abstract A complementary semiconductor device includes P-and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.
Inventors
- 👤 Hideharu Egawa
- 👤 Koji Matsuki
- 👤 Yasoji Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 23:21
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
126 words
A method for manufacturing a complementary semiconductor device comprising: forming P- and N-type semiconductor regions in a semiconductor substrate of one conductivity type having a low impurity concentration; forming impurity layers by doping the same conductivity type impurity into predetermined portions of said P- and N-type semiconductor regions; forming gate regions to partially cover each of the impurity layers, said gate regions including polycrystalline silicon layers of the same conductivity type; and simultaneously forming source and drain regions in the respective P- and N-type semiconductor regions to form N- and P-channel type field effect transistors wherein said impurity layer is formed by doping that amount of impurity which is enough to control the threshold voltages of the N- and P-channel type transistors to a desired level.
Claim 2
Independent Claim
126 words
A method for manufacturing a complementary semiconductor device comprising: forming P- and N-type semiconductor regions in a semiconductor substrate of one conductivity type having a low impurity concentration; forming impurity layers by doping the same conductivity type impurity into predetermined portions of said P- and N-type semiconductor regions; forming gate regions to partially cover each of the impurity layers, said gate regions including polycrystalline silicon layers of the same conductivity type; and simultaneously forming source and drain regions in the respective P- and N-type semiconductor regions to form N- and P-channel type field effect transistors wherein said impurity layer is formed by doping that amount of impurity which is enough to control the threshold voltages of the N- and P-channel type transistors to a desired level.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-07-27 | 1985-01-26 | 1985-07-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-07-27 | 1989-01-26 | 1989-07-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-07-27 | 1993-01-26 | 1993-07-28 | $7700.00 | Window Closed / Lapsed |