Abstract A method of forming an enhancement mode and a depletion mode transistor on a single substrate of a first conductivity type wherein each of the transistors has a pair of second conductivity type source and drain regions which are separated by a channel region and wherein an insulating layer is present on the surface of the substrate. The improvement comprises the steps of introducing a first conductivity type impurity in the substrate at the surface thereof, except in the channel region of the depletion mode transistor, reducing the amount of introduced impurity in the channel region of the enhancement mode transistor, producing contact holes in the insulating layer above the respective source and drain regions, and forming the respective gate, source and drain electrodes. The process eliminates field inversion without the necessity of a substrate bias and provides an automatic alignment of the channel of the enhancement mode transistor and the region of reduced concentration of the introduced impurity.
IN A METHOD OF SIMULTANEOUSLY FORMING A PAIR OF TRANSISTORS, ONE OF WHICH IS OPERATIVE IN A FIRST MODE AND THE SECOND OF WHICH IS OPERATIVE IN A SECOND MODE, ON A SINGLE SUBSTRATE OF A FIRST CONDUCTIVITY TYPE WHEREIN EACH OF THE TRANSISTORS HAS A PAIR OF SECOND CONDUCTIVITY TYPE SOURCE AND DRAIN REGIONS SEPARATED BY A CHANNEL REGION AT A SURFACE OF SAID SUBSTRATE AND WHERE AN INSULATING LAYER IS PRESENT ON SAID SURFACE OF THE SUBSTRATE, THE IMPROVEMENT COMPRISING THE STEPS OF INTRODUCING A FIRST CONDUCTIVITY TYPE IMPURITY IN THE SUBSTRATE AT THE SURFACE EXCEPT IN CERTAIN REGIONS THEREIN, REDUCING THE AMOUNT OF IMPURITY IN SELECTED PORTIONS OF THE IMPURITY CONTAINING REGIONS TO FORM A FIRST SET OF REGIONS HAVING NO IMPURITY THEREIN, A SECOND SET OF REGIONS HAVING A REDUCED CONCENTRATION OF IMPURITY THEREIN AND A THIRD SET OF REGIONS HAVING A NONREDUCED CONCENTRATION OF IMPURITY THEREIN, PRODUCING CONTACT HOLES IN THE INSULATING LAYER OF THE RESPECTIVE SOURCE AND DRAIN REGIONS, AND FORMING THE RESPECTIVE GATE, SOURCE AND DRAIN ELECTRODES.
Claim 2
Dependent Claim
174 words
IN A METHOD OF SIMULTANEOUSLY FORMING A PAIR OF TRANSISTORS, ONE OF WHICH IS OPERATIVE IN A FIRST MODE AND THE SECOND OF WHICH IS OPERATIVE IN A SECOND MODE, ON A SINGLE SUBSTRATE OF A FIRST CONDUCTIVITY TYPE WHEREIN EACH OF THE TRANSISTORS HAS A PAIR OF SECOND CONDUCTIVITY TYPE SOURCE AND DRAIN REGIONS SEPARATED BY A CHANNEL REGION AT A SURFACE OF SAID SUBSTRATE AND WHERE AN INSULATING LAYER IS PRESENT ON SAID SURFACE OF THE SUBSTRATE, THE IMPROVEMENT COMPRISING THE STEPS OF INTRODUCING A FIRST CONDUCTIVITY TYPE IMPURITY IN THE SUBSTRATE AT THE SURFACE EXCEPT IN CERTAIN REGIONS THEREIN, REDUCING THE AMOUNT OF IMPURITY IN SELECTED PORTIONS OF THE IMPURITY CONTAINING REGIONS TO FORM A FIRST SET OF REGIONS HAVING NO IMPURITY THEREIN, A SECOND SET OF REGIONS HAVING A REDUCED CONCENTRATION OF IMPURITY THEREIN AND A THIRD SET OF REGIONS HAVING A NONREDUCED CONCENTRATION OF IMPURITY THEREIN, PRODUCING CONTACT HOLES IN THE INSULATING LAYER OF THE RESPECTIVE SOURCE AND DRAIN REGIONS, AND FORMING THE RESPECTIVE GATE, SOURCE AND DRAIN ELECTRODES.
Claim 3
Dependent Claim
67 words
The method according to claim 1 wherein said first mode is an enhancement mode and said second mode is a depletion mode and wherein said first set of regions is the channel region of the depletion mode transistor and wherein said second set of regions is the channel region of the enhancement mode transistor and wherein said third set of regions includes the substrate between said transistors.
Claim 4
Dependent Claim
42 words
The method according to claim 2 wherein the impurity introducing step comprises covering the channel region of the depletion mode transistor with an ion implantation mask and exposing the surface of the unit to a beam of first conductivity determining type ions.
Claim 5
Dependent Claim
22 words
The method of claim 1 wherein the impurity amount reducing step comprises growing an oxide layer over said second set of regions.